12 b 50 MS/s 0.18 μm CMOS SAR ADC based on highly linear C‐R hybrid DAC

Abstract

A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted capacitor array and the remaining lower bits based on reference segment voltages, which are obtained from a simple resistor string. The reduced number of unit capacitors enables the use of larger unit capacitance, resulting in improved matching accuracy. In the C-R hybrid DAC, an input range scaling technique, which matches a full-scale input range to the reference voltage range, implements the binary-weighted SAR operation without additional capacitors and reference voltages. The DAC linearity is improved considerably through the processinsensitive capacitor-array layout, which cancels out oxide-gradient errors. The prototype ADC in a 0.18 μm CMOS process demonstrates measured differential and integral non-linearities within 0.71 LSB and 0.85 LSB at 12 b, respectively, with a maximum signal-to-noise-anddistortion ratio and a spurious-free dynamic range of 64.3 and 74.7 dB at 50 MS/s, respectively. The ADC occupies an active die area of 0.17 mm 2 and consumes 2.63 mA with a 1.8 V supply voltage.

A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer

“…Reference [7] did not account for the off-chip two-stage PGA when calculating the power consumption. The measured data of [22] and [23] do not suffer from the PGA's influence. The work described here is the only one that integrated the PGA and RV-Buffer with the ADC, and all three were included when measured.…”

Analog to Digital Converters (ADC): A Literature Review

“…In fig 7, the survey is plotted on the published articles based on SAR ADC till 2019 in VLIS and till 2020 in ISSCC, taken from the survey [78]. The prevailing research proves that the hybrid ADCs [65][66][67] architecture is more advantageous for enhancement in terms of speed and for low power operations [68]. The hybrid ADCs [79][80][81][82] have different combinations and blocks as per the applications demand.…”