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This study presents a high-efficiency low-noise pulse-width modulation (PWM) DC-DC buck converter based on multi-partition switching for mobile system-on-a-chip applications. A multi-partition switching technique is employed for the control of large current driving switches to minimise the switching noise. In addition, a PWM control with a switching frequency of 2 MHz is applied for the driving of output stage with a heavy load to optimise the power efficiency. The prototype DC-DC buck converter with an active die area of 0.28 mm 2 was implemented using a 0.18 µm bipolar-CMOS-DMOS (BCD) process. The peak power efficiency is 93%, while supplying an output current of 200 mA and an output voltage of 1.8 V.

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A calibrated 10 b 5 MS/s 28 nm CMOS successive-approximationregister ADC based on an integer-based split capacitor array is presented. The proposed ADC employs a split capacitor array to optimise the overall power consumption, chip area and linearity performance. An attenuation capacitor between two capacitor arrays is implemented with an integer multiple of unit capacitors rather than a fraction of unit capacitors. The proposed calibration of capacitors reduces the non-linearity error caused by device mismatches in the conventional split capacitor array. The measured prototype ADC which has an active die area of 0.063 mm 2 shows a maximum signal-to-noise-anddistortion ratio and spurious-free dynamic range of 59.25 and 70.44 dB, respectively, and consumes 42.5 μW at 0.7 V and 5 MS/s. Moreover, the measured differential non-linearity (NL) and integral NL are within 0.36 and 0.52 least significant bit, respectively, after calibration.

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