A range-scaled 13b 100MS/s 0.13&amp;#x03BC;m CMOS SHA-free ADC based on a single reference

Hwang, Dae‐Youn; Song, Jung-Eun; Nam, Sang-Pil; Kim, Hyojin; An, Tai-Ji; Kim, Kwangsoo; Lee, Seung‐Hoon

doi:10.1109/isocc.2011.6138646

Cited by 8 publications

(2 citation statements)

References 6 publications

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“…To overcome these disadvantages, a SHA-free pipeline ADC has been proposed, as shown in Fig. 1(b) [9][10][11][12][13][14]. However, the SHA-free architecture suffers from a sampling-time mismatch due to a difference in input sampling paths between the first-stage multiplying digital-to-analog converter (MDAC) and the flash ADC.…”

Section: Introductionmentioning

confidence: 99%

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

Park¹,

Jeong²,

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Section: Introductionmentioning

confidence: 99%

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

Park¹,

Jeong²,

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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“…In the conventional pipeline ADCs, a dedicated input sample-and-hold amplifier (SHA) has been employed to reduce a sampling-time mismatch between the first-stage multiplying digital-to-analog converter (MDAC) and the flash ADC. For low power and small chip area, various SHA-free pipeline ADCs have been proposed [6][7][8][9][10][11][12]. However, previously reported SHA-free ADCs partially resolve the problems by a sampling-time mismatch with extra digital logic or inventive layout techniques for sampling networks.…”

Section: Introductionmentioning

confidence: 99%

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

Park¹,

An²,

Cho³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This work proposes a 12b 100 MS/s 0.11 µm CMOS three-step hybrid pipeline ADC for highspeed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dualchannel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a 0.11 µm CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of 1.34 mm 2 and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

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Wang

2017

Analog Circuits and Signal Processing

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A range-scaled 13b 100MS/s 0.13μm CMOS SHA-free ADC based on a single reference

Cited by 8 publications

References 6 publications

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

Reference Voltage Buffer

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