This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s.
This paper presents a broadband frequency quadrupler (FQ) implemented with a standard 130-nm SiGe BiCMOS process. Two broadband push-push frequency doublers (×2) operate at an input frequency of 32.5–55 GHz and 65–110 GHz, respectively. To properly drive the two doublers with enough input power and bandwidth, two transformer coupled power amplifiers (PAs) have been adopted. The former power amplifier is based on a neutralized capacitor structure and the latter is based on a transformer topology. A nonlinear device model and a systematic methodology to generate maximum power at second harmonic are proposed. By manipulating the device nonlinearity and optimizing the magnetically and capacitively coupled resonator (MCCR) matching networks, optimum conditions for harmonic power generation are provided. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range and a high energy efficiency η of 3.7% at 210 GHz.
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