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This paper discusses the configuration of an ATM(Asynchronous TmnsferMode) switching networkwirh a shared buffer memory switch (SBMS) which has the potential to provide good trafic characteristics and ensy Lsf hplemenmioa The scaling factors of the ATM switching network under a conditwn of mired applicatwns are discussed first. Then the SBMS as the unit element of the multi-stage switching network is described, and its performance evaluation andexperimental data are introduced. The data indicate excellent performance under burst cell arrival conditwn. Last, a concept of a large scale ATM switching network configuratwn with multi-stage switches is proposed. The nonblocking conditwn in ATM multi-stage switching network as an alternative resoutce management scheme is described.In the fmt phase, the ratio of the subscriber is less than 0.5%. The business user will be the main applicant for this service. The required throughput is about 4Gb/s which corresponds to the switching network with about thirty ports of lSOMb/s line. This means that the single unit switch is sufficient for the switching network of this phase.In the second phase, the ratio is around 10%. This is the penetrating phase. Required throughput is about lSOGb/s which corresponds to the switching network with lo00 ports. This means that a multi-stage switching network is required.

In the 21st century, 10-30 Mbps video services will be the main traffic services of B-ISDN. Therefore, bandwidth control is effective for dividing a 150-Mbps line into the call bandwidths. A shared buffer-type ATM switch with this function can be achieved by queueing call by call and by reading out cells from the queues according to the bandwidth control table sequence. When the traffic is random with utilization of 0.9, the switch with 128 -5 12 queues on the 4000cell shared buffer has sufficiently small cell loss characteristics.Multiqueueing technology is provided by embedded RAMs which point to the first addresses and last addresses of the queues. Queue length control, which limits each queue length, for multiqueueing is provided by the embedded RAMs. A one-board switch with 128 queues on a 4000-cell shared buffer is developed.