Large-scale ATM multistage switching network with shared buffer memory switches

Sakurai, Y.; Ido, N.; Gohara, S.; Endo, N.

doi:10.1109/35.64729

Cited by 55 publications

(6 citation statements)

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“…When , our simulation failed to generate any blocking event, indicating that an expansion or speedup factor of two is probably enough to build a close-to-nonblocking switch. This compares well with the results in the previous section that a speedup factor of about 3 [see (6)] and an expansion factor of about 6 [see (3)] are needed to build a nonblocking switch.…”

Section: Simulation Resultssupporting

confidence: 91%

“…Nonblocking Condition 2: The Clos network with speedup factor is strictly nonblocking for packet switching if and only if (6) Proof: Consider a request . Let be one of the inputs of a first-stage switch module and be one of the outputs of a third-stage switch module .…”

Section: B Switch With Speedup Factormentioning

confidence: 99%

“…Melen and Turner laid out the foundation for the study of multirate networks [4] in which each link can be used by a number of connections as long as the sum of their data rates does not exceed that of the link. Among many network configurations, the Clos network, in particular, has been widely proposed as a way to build scalable fast-packet/asynchronous transfer mode (ATM) switches [3], [7], [6].…”

Section: Introductionmentioning

confidence: 99%

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Blocking and nonblocking multirate Clos switching networks

Liew

Chan

1998

IEEE/ACM Trans. Networking

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Abstract-This paper investigates in detail the blocking and nonblocking behavior of multirate Clos switching networks at the connection/virtual connection level. The results are applicable to multirate circuit and fast-packet switching systems. Necessary and sufficient nonblocking conditions are derived analytically. Based on the results, an optimal bandwidth partitioning scheme is proposed to reduce switch complexity while maintaining the nonblocking property. The blocking behavior of blocking switches supporting multicast connections is investigated by means of simulation. We propose a novel simulation model that filters out external blocking events without distorting the bandwidth and fanout (for multicasting) distributions of connection requests. In this way, the internal blocking statistics that truly reflect the switch performance can be gathered and studied. Among many simulation results, we have shown that for point-to-multipoint connections, a heuristic routing policy that attempts to build a narrow multicast tree can have relatively low blocking probabilities compared with other routing policies. In addition, when small blocking probability can be tolerated, our results indicate that situations with many large-fanout connection requests do not necessarily require a switch architecture of higher complexity compared to that with only point-to-point requests.

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Section: Simulation Resultssupporting

confidence: 91%

Section: B Switch With Speedup Factormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Blocking and nonblocking multirate Clos switching networks

Liew

Chan

1998

IEEE/ACM Trans. Networking

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“…The location of buffers in an SE is crucial in the throughput, delay, and cost of the switch. Input, output, and shared buffering are among the types of internal buffering whose performances have been widely studied by researchers in multiprocessors systems [1][2][3] and communications networks [4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

An accurate performance model of shared buffer ATM switches under hot spot traffic

Saleh

Atiquzzaman

1999

Computer Communications

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Asynchronous transfer mode (ATM) switches based on shared buffering are known to have better performance and buffer utilization than input or output queued switches. Shared buffer switches do not suffer from head of line blocking which is a problem in simple input buffering. Shared buffer switches have previously been studied under uniform and unbalanced traffic patterns. However, due to the complexity of the model, the performance of such a switch, in the presence of a single hot spot, has not been fully explored. In this article, we develop a model for a multistage ATM switch constructed of shared buffer switching elements and operating under a hot spot traffic pattern. The model is used to study the switch performance in terms of the throughput, cell delay, cell loss probability and the optimal buffer size. ᭧

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“…Reliability of the bus is very crucial to achieve correct path assignments. The switch proposed in [6] uses only one switch module, i.e., the memory switch. Shared buffers are provided at the output of each switch module.…”

Section: Introductionmentioning

confidence: 99%

A large scale ATM switching network with sort-banyan switch modules

Hui

Lee

[Conference Record] GLOBECOM '92 - Communications for Global Users: IEEE

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This paper proposes a large scale broadband self-routing switching network based on the three-stage construction of sort-banyan switch modules. The proposed switching network uses only one kind of module, preserves the cell sequencing of a service, and is robust for all patterns of load on the ports. A multistage three-phase algorithm is designed to control the delivery of cells. The switching iietwork is input queued and delivers at most one cell in a cell time to each output port from one of the input ports which request cell delivery to that output port. The maximum throughput of the switching network is shown to be 0.458 which is about 78% of that of a single-stage sort-banyan switching network. With a buffer size of 20 cells, we can achieve a 40 percent loading with almost no buffer overflow. Parallelism is easily achieved by having multiple switching planes. With 4 switching planes, we show that the network is close to being output-queued.

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Large-scale ATM multistage switching network with shared buffer memory switches

Cited by 55 publications

References 1 publication

Blocking and nonblocking multirate Clos switching networks

Blocking and nonblocking multirate Clos switching networks

An accurate performance model of shared buffer ATM switches under hot spot traffic

A large scale ATM switching network with sort-banyan switch modules

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