A large scale ATM switching network with sort-banyan switch modules

Hui, J.Y.; Lee, T.

doi:10.1109/glocom.1992.276505

Cited by 16 publications

(6 citation statements)

References 8 publications

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“…Simple interconnection of these smaller switches creates several stages of queueing delay, and results in severe performance degradation if congestion occurs at intermediate modules. For instance, the Clos connection pattern shown in [4] has only 46% throughput.…”

Section: Introductionmentioning

confidence: 99%

A large scalable ATM multicast switch

Law¹,

Leon-Garcia²

1997

IEEE J. Select. Areas Commun.

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This paper focuses on designing a large N 2 N high-performance broad-band ATM switch. Despite advances in architectural designs, practical switch dimensions continue to be severely limited by both the technological and physical constraints of packaging. Here, we focus on augmentation in a "single-switch" design: we provide ways to construct arbitrarily large switches out of modest-size components and retain overall delay/throughput performance. We propose a growable switch architecture based on several key principles: 1) the knockout principle exploits the statistical behavior of cell arrivals, and thereby reduces the interconnect complexity; 2) output queueing yields the best possible delay/throughput performance; 3) distributed control in routing (multicast) cells through the interconnect fabric without internal path conflicts; and 4) simple basic building blocks facilitate scalability. Other attractive features of the proposed architecture include: 1) intrinsic broadcast and multicast capabilities; 2) built-in priority sorting functionality; and 3) the guarantee of first-in, first-out cell sequence. To achieve 10 014 cell loss probability, only maximum size 32 2 16 basic building modules are required, and no crossover interconnects exist between modules in a three-dimensional configuration.

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Section: Introductionmentioning

confidence: 99%

A large scalable ATM multicast switch

Law¹,

Leon-Garcia²

1997

IEEE J. Select. Areas Commun.

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“…This paper considers cell-level path allocation, and, specifically, the problem of implementing a cell-level algorithm for path allocation in the channel-grouped three stage network of Fig. 1 [5]- [7]. The algorithm described here requires fewer iterations than that in [6], does not require input buffering (which degrades the throughput), unlike [7], and is fairer than that presented in [5], in addition to readily supporting intermediate channel grouping.…”

Section: Introductionmentioning

confidence: 99%

A three-stage ATM switch with cell-level path allocation

Collier

1997

IEEE Trans. Commun.

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Abstract-A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to here as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described here.

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“…For the capability of modular growth, there are two methods to fulfill [ll]: (1) using the Knockout principle: generalization from a single output to group outputs [12] and (2) using the intcrconncction fabric: concept of multistage interconnection networks [13]. For a unicast switch [14], self-routing and output port contention resolution should be performed in a distributed way so that the centralized processing will not become a bottleneck to construct a large switch.…”

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of a growable multicast ATM switch

Wang

Cheng²

Proceedings of INFOCOM '97

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I n ihis paper, we design and analyze a growable multicast ATM switch. It can grow to a large size since both cell routing and contention resolution are designed t o distribute over switch elements, and the switch structure is modular. The output ports arc partitioned into groups t o p e r m i t sharing of routing paths. The concept of group routing helps reduce an order of magnitude of sufitch elements. A two-stage switch architecture is described to illustrate our design principle. The switch can be easily expanded i o a larger site b y using more stages. The performance analysis of Ihe switch i n terms of cell loss rate, cell dclay, mean queue length, mean waiting time, and throughput is conducted using the M / G e o n i / l model. Experimental results show that the proposed ATM switch not only meets the ATM performance requirements either f o r unicasting or multicasting but also uses fewer switch elements and has less delay than other comparable switches.put port controllers (IPC1, IPC2), grouping networks (GN1, GAr2), and output port controllers (OPC). Each I P C (IPC1 or 1Pc.1) accepts arrival cells, uses the arrival routing information ( V C I ) to look up the routing table, and attaches new routing information to the front of the ccll to route it in thc grouping network. A GN (GN1 or GJV.I) sends multicast cclls to 932 8a.2.1

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A large scale ATM switching network with sort-banyan switch modules

Cited by 16 publications

References 8 publications

A large scalable ATM multicast switch

A large scalable ATM multicast switch

A three-stage ATM switch with cell-level path allocation

Design and performance analysis of a growable multicast ATM switch

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