Shared buffer memory switch for an ATM exchange

<title>Efficient input queuing and cell scheduling scheme for scalable ultrabroadband optoelectronic ATM switching</title>

“…In the second iteration, two entries, (2,1) and (1,2) are selected since w12 = W21 = 3/2, the heaviest weight.…”

Numerical methods for analysis of multiflow queuing systems with virtual partition of a common buffer

“…Because of lacking space, we will omit detailing of the results obtained in this area and just mention the studies [3][4][5][6][7][8][9][10], which include an extensive bibliography.…”

Mesh of Trees Topology for Output Queued Switches: Trading Speed-up with a Pipeline Technique

“…Cells involved in such an event are lost, causing a local resources waste (one or more idle cycles, even if in presence of data to be processed) and a system misuse (packets need to be retransmitted from the originating source): it is then necessary to serialize in some ways all the competing cells. Probably the most naive solution [5,6] is to use a shared memory, where inputs write their cells, and outputs read a suitably chosen subset of them (see figure 1(a) for a very simple graphical representation). Even if recent studies [7,8] have shown that this architecture, combined with a hierarchy of parallel memories, is practical and capable to guarantee quality of service, historically it was not taken into account, for the technological impossibility in having huge and extremely fast memories as needed to serve a high number of inputs/outputs at a fast enough speed.…”