This paper describes how a state of the art successfu~'y incorporated into a 0'6um process' The circuits or cells designed on either process can be realized on the new process.ple where possible the interaction of the CMOS devices with the bipolar devices. For example, neither the MOS gate for the polysilicon layers of the bipolar transistor as all these cies and sheet resistances. To combine these would require an unacceptable level of compromise on device paramebipolar process designed for R F applications has been po~ysi~icon nor the top capacitor polysilicon were used resultant BiCMoS process has the feature that products, po~ysi~icon layers are incompatible in terms of dopant spe-
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