This paper describes how a state of the art successfu~'y incorporated into a 0'6um process' The circuits or cells designed on either process can be realized on the new process.ple where possible the interaction of the CMOS devices with the bipolar devices. For example, neither the MOS gate for the polysilicon layers of the bipolar transistor as all these cies and sheet resistances. To combine these would require an unacceptable level of compromise on device paramebipolar process designed for R F applications has been po~ysi~icon nor the top capacitor polysilicon were used resultant BiCMoS process has the feature that products, po~ysi~icon layers are incompatible in terms of dopant spe-
Abstr actThis paper describes a 0.35um BiCMOS process, the key aspect of which is the range of applications served by the process. To service the varied requirements, the process is designed to support high yielding, high performance active devices, high precision, well-matched passive elements, plus a variety of options such as thick metal, high-Q inductors. The process is also compatible with an existing dualvoltage CMOS process.The paper describes some novel features such as the NPN collector design, process thermal sequence and presents results from all the devices and a PLL circuit.
This paper evaluates the hot-carrier performance of the n-channel high-voltage (30 V) MOSFET device. This device is widely used in high-voltage linear products. It can withstand 30 V across any two terminals. This large voltage range requires thorough hot-carrier analysis, investigating potential hot-carrier mechanisms not believed to have been previously explored in the literature. It is established that two different hot-carrier generation mechanisms are occurring: one at I SUB(max) and another at I KIRK . These are investigated through combined device parametric, technology computer-aided design (TCAD) simulation, and hot-carrier reliability data.Index Terms-Degradation mechanism, device optimization, hot carrier. I. DEVICE DESCRIPTIONI N THIS PAPER, we consider a 30-V double diffused drain CMOS integrated into an existing 5-V CMOS process. A schematic of this device is shown in Fig. 1. It features V TH = 1.2 V, L = 6.0 µm, and t OX = 800 A. The lightly doped drain overlaps the gate poly by 1 µm, and the heavily doped contact region is spaced 1.1 µm from the poly edge. For compatibility with the 5-V CMOS, the lightly doped drain is quite shallow, i.e., Xj < 1 µm. For analog circuits, high output resistance and, hence, low I SUB are desirable. This requires the graded drain doping to be low. This device differs from those used in previous high-voltage MOS (HV-MOS) and laterally diffused MOS (LDMOS) studies [1]-[8], most particularly in t OX . II. DEVICE CHARACTERIZATIONParametric analysis produces a substrate current I SUB characteristic at stress V D = 36 V, as shown in Fig. 2. Both ON-state and OFF-state breakdown voltages are > 40 V. The normal I SUB(max) is observed at V G = 8 V and is labeled as "A". An unexpected exponential increase in I SUB is noted in region "B" and is referred to as I KIRK due to its high drain current and low graded drain doping origin [8]- [10].From simulation, shown in Fig. 3, the generated substrate current in region A is the hole current from impact ionization (II) at the drain region under that gate, i.e., a regular MOSFET hot-carrier phenomenon. This II is subsurface and is a distance from the vertical electric field. Fig. 1. Cross section schematic of the 30-V nMOSFET.Fig. 2. Substrate current I SUB characteristic at V D = 36 V.Fig. 3. Region of II by the drain (A) at V D = 30 V and V G = 8 V.of II from the channel region differs from the submicrometer MOSFET situation.The generated substrate current in region B increases with both increasing V D and V G . Simulation shows that this hole current originates from a region of II at the drain contact, as shown in Fig. 4. The transition from graded drain to heavily doped drain causes a large lateral electric field that results in II. This II is a distance from the intrinsic region of the device.1530-4388/$25.00
Flat-band voltage Bulk threshold parameter Channel length modulation Oxide thickness Surface mobility Maximum carrier drift velocity Mobility modulation ~o d y effect mobility parameter Linear GAMMA parameter VDS dependent mobility term Static drain feedback Body effect static drain feedback Output conductance parameter Zero bias gate drive coefficient vDS bias gate drive coefficient VBS bias gate drive coefficient Weak inversion fitting parameter Channel length reduction parameter Channel width reduction parameter Draia/source resistance parameter
An antimony buried layer is developed for a 0.35um BiCMOS process. Antimony buried layers can cause stacking fault defects to propagate through the epilayer deposited on it. These can result in device failure mechanisms such as collectoremitter pipes etc. This paper outlines the understanding of this defect mechanism derived by a combination of physical analysis combined with process simulation. Its relationship to the low solid solubility of antimony is established. In addition observed antimony dose loss from the buried layer is described.
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