NASA’s Mars 2020 (M2020) rover mission includes a suite of sensors to monitor current environmental conditions near the surface of Mars and to constrain bulk aerosol properties from changes in atmospheric radiation at the surface. The Mars Environmental Dynamics Analyzer (MEDA) consists of a set of meteorological sensors including wind sensor, a barometer, a relative humidity sensor, a set of 5 thermocouples to measure atmospheric temperature at ∼1.5 m and ∼0.5 m above the surface, a set of thermopiles to characterize the thermal IR brightness temperatures of the surface and the lower atmosphere. MEDA adds a radiation and dust sensor to monitor the optical atmospheric properties that can be used to infer bulk aerosol physical properties such as particle size distribution, non-sphericity, and concentration. The MEDA package and its scientific purpose are described in this document as well as how it responded to the calibration tests and how it helps prepare for the human exploration of Mars. A comparison is also presented to previous environmental monitoring payloads landed on Mars on the Viking, Pathfinder, Phoenix, MSL, and InSight spacecraft.

Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.Index Terms-Analog programmable very large-scale integration (VLSI), early vision chips, silicon retinas.

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes.

This paper presents an analysis of the stability and convergence properties of the full signal range (FSR) CNN model. These properties are demonstrated to be similar to those of the Chua‐Yang model and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. In this modified CNN model the dynamic range of the cell state variables equals the dynamic range of the cell output variables and is invariant with the application. This feature results in simpler circuit implementations, thus allowing higher cell densities and improving the robustness of CNN integrated circuits. The FSR CNN model is particularly well suited for programmable CNN integrated circuits.

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. Onchip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-m single-poly double-metal technology and features 2-s operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations. Index Terms-Analog array processors, cellular neural networks, focal plane processors, vision chips. I. INTRODUCTION C ONVENTIONAL image-processing systems use a charge-coupled device (CCD) camera for parallel acquisition of the input image and serial transmission of the digitalized image to a separate processing element. It results in huge data rates which conventional computers are not capable of analyzing in real-time. For instance, a color 512 512 pixel camera delivers about 20 MB/s, for Manuscript

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