A VLSI-oriented continuous-time CNN model

Abstract

This paper presents an analysis of the stability and convergence properties of the full signal range (FSR) CNN model. These properties are demonstrated to be similar to those of the Chua‐Yang model and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. In this modified CNN model the dynamic range of the cell state variables equals the dynamic range of the cell output variables and is invariant with the application. This feature results in simpler circuit implementations, thus allowing higher cell densities and improving the robustness of CNN integrated circuits. The FSR CNN model is particularly well suited for programmable CNN integrated circuits.

On global exponential stability of standard and full‐range CNNs

“…Advantages in the VLSI implementation of CNN chips with a large number of neurons have been obtained by using the ISR model of CNNs [2,3]: where m 0 is a constant and the diagonal mapping…”

“…The ideal hard-limiter h now constrains the state variables x i of (F) to evolve within K , i.e. we have |x i (t)| 1 for all t. Furthermore, x = G(x) and (I) reduces to the FR model of CNNs [2,3]:ẋ…”

“…By means of techniques from ordinary differential equations, a sound foundation to models (S) and (I) has been given in [1,3], respectively. A rigorous mathematical foundation of model (F) can be obtained by using tools from the theory of differential inclusions.…”

“…In defining CNN models (I) and (F), we have followed the treatment in [3]. Note that for increasing m, model (I) can be seen as a transition from (S) to (F).…”

Pattern formation on the prototype complex-cell CNN-UM chip (CACE1K)

“…The evolution of the state variable (x) is also determined by a self-feedback and by the feed-forward action of the stored input (u) and bias (z) values. There is a voltage limiter (g) for implementing the full signal range (FSR) property of the implemented CNN-UM resulting in the very same state variable that is the output of the system [6].…”