A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

Cembrano, Gustavo Liñán; Rodríguez-Vázquez, Á.; Galan, R.; Jimenez-Garrido, F.; Espejo, S.; Domínguez-Castro, R.

doi:10.1109/jssc.2004.829931

Cited by 73 publications

(52 citation statements)

References 17 publications

(29 reference statements)

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“…Intensive research on specialized high-speed analog vision chips with reduced supply power is observed. Confirmation of this fact can be found in the literature, where the analog vision chips [6][7][8][9][10][11][12][13][14][15][16] are faster and consume less power than the digital realizations [17][18]. The remainder of this paper is devoted to a general discussion, in Sec.…”

Section: Introductionmentioning

confidence: 55%

“…In this kind of matrix only simple vision processors occupying a small area can be used, otherwise the size of the entire array, and consequently the cost of its production will become excessively large. Examples of implementations of such systems in 0.35 µm CMOS technology are presented in [6,9,15], and [27][28][29][30][31].…”

Section: Architecture With An Embedded Array Of Processorsmentioning

confidence: 99%

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Analogue CMOS ASICs in Image Processing Systems

Jendernalik¹,

Blakiewicz²,

Handkiewicz³

et al. 2013

Metrology and Measurement Systems

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In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.

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Section: Introductionmentioning

confidence: 55%

Section: Architecture With An Embedded Array Of Processorsmentioning

confidence: 99%

Analogue CMOS ASICs in Image Processing Systems

Jendernalik¹,

Blakiewicz²,

Handkiewicz³

et al. 2013

Metrology and Measurement Systems

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“…The next generations of the programmable vision-chips, designed in multiple instruction multiple data (MIMD) or single instruction multiple data (SIMD) architectures, were able to perform several image algorithms [1][2][3][4][5]. The newest chips have fully programmed architectures with parallel analogue data processing of significantly reduced processing time [6][7][8][9]. Although the development in vision-chip implementations is impressive, supply power consumption and image processing speed still need to be improved.…”

Section: Introductionmentioning

confidence: 99%

“…A relatively small photo-current in the pA range, generated by the photo-sensors, can be converted to voltage with an amplitude of about 1 V in order to allow processing in the voltage-mode analogue processors [10][11][12][13][14][15][16][17]. Another approach is to directly amplify the photo-current to the µA level, in order to be processed in the current-mode analogue processors [5][6][18][19]. In such circuit solutions, the main part of supply power is consumed by the analogue processors.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos Technology

Jendernalik¹,

Jakusz²,

Blakiewicz³

et al. 2012

Metrology and Measurement Systems

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The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 µm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 × 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.

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“…However, it is important to understand that this chip is positioned as a 'CNN-inspired' SIMD array and the performance is estimated from the CNN computational model perspective. Indeed, despite providing 330 GOPS performance, simple convolution operations such as smoothing and Sobel edge detection are reported to take approximately 4µs (with required calibrations) [11]. At the same time, the ASPA chip with 2.4 MOPS/cell executes these operations in 2.7µs and 5.5µs correspondingly (at 37.5 MHz).…”

Section: Introductionmentioning

confidence: 99%