H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced about 20 ~ 25%. This paper also proposes new instructions for the integer transform. The proposed instructions can execute one dimension forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.
With the rapid progress of semiconductor technology, Application Specific Instruction-set Processor (ASIP), which adopts high performance and low power of ASIC and flexibility of DSP, has become increasingly important. In this paper, the Video Specific Instruction-set Processor (VSIP) is presented. VSIP has special instructions and co-processors for computation intensive parts in video signal processing, such as inter prediction, entropy coding, de-blocking filter, etc. The proposed VSIP has been thoroughly verified using an FPGA board having the XilinxTM Virtex II. The proposed VSIP can implement a H.264/AVC decoder. The proposed VSIP is one of promising solutions for video signal processing.
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