Novel Instructions and Their Hardware Architecture for Video Signal Processing

Abstract

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced about 20 ~ 25%. This paper also proposes new instructions for the integer transform. The proposed instructions can execute one dimension forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.

A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications

“…Among various coding tools in H.264/AVC, the in-loop deblocking filtering has the most significant impact on the visual quality improvement [20,21]. To reduce the blocking artifact, the in-loop deblocking filter adaptively conducts the filtering along the boundaries of each 4×4 block based on the BS, the quantization parameter (QP) and the content of the block.…”

VSIP : Implementation of Video Specific Instruction-set Processor

“…A large number of instruction cycles is required to implement the in-loop deblocking filter and intra prediction with the existing packed instructions that execute packed operations between two registers. Hence, we have previously proposed three horizontal addition (HADD) instructions [3]. Fig.…”

“…However, a programmable DSP should solve the disadvantages, such as cost, size, and power consumption. ASIP can compromise advantages of custom ASIC chips and general DSP chips [1]- [3]. Multimedia signal processing technology has been developed with the progress of semiconductor technology.…”

Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System

“…Tests show that, with the methods proposed in this paper, the performance of MC is improved by 60%, Deblocking by 73%, and IDCT-IQ by 88.5% in the typical case and by 60%, 69% and 88.5% in the worst case, compared with those of XPP PACT. Compared with some ASIC solutions [11], [16], [17], the performance of MC is improved by 70% in the typical case and 74% in the worst case, IDCT by 17% (both in the typical and worst case), while those of Deblocking are nearly the same. Relying on all these improvements, real-time decoding (1920 × 1080@30 fps) of H.264 HiP@ Level 4 could be realized on REMUS when exploiting a 200 MHz working frequency.…”

“…For IDCT-IQ, XPP PACT and ASSP-IDCT [17] only focus on the parallelism of intrablocks, while little attention is given to the parallelism of inter-blocks.…”