Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System

Geng, Tongsheng; Liu, Leibo; Yin, Shouyi; Zhu, Min; Wei, Shaojun

doi:10.1587/transinf.e93.d.3223

Cited by 10 publications

(6 citation statements)

References 14 publications

(14 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other studies, such as parallelization of computeintensive tasks in H.264 based on reconfigurable multimedia system [11], have also shown that the block-based wordlevel calculations comprise a majority of the decoding workloads in all the video decoding standards. For instance, an experiment of H.264 decoding is performed on a RISC processor to measure the workloads of MC, DF, and inverse quantization and transformation (IQT).…”

Section: Algorithm Analysismentioning

confidence: 99%

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Liu

Wang

Chen

et al. 2016

IEICE Trans. Inf. & Syst.

Self Cite

View full text Add to dashboard Cite

SUMMARYThis paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 × 16 multi-functional processing elements (PEs), is used to accelerate computeintensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.

show abstract

Section: Algorithm Analysismentioning

confidence: 99%

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

Liu

Wang

Chen

et al. 2016

IEICE Trans. Inf. & Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…It has been shown in [11] that the block-based word-level calculations comprise a majority of the decoding workloads. For instance, an H.264 decoding application is performed on a RISC processor and the measured MC, deblocking, and Inverse Quantization and Transformation (IQT) workloads account for more than 75% of the total workload as illustrated in Fig.…”

Section: Algorithm Analysis and Design Considerationmentioning

confidence: 99%

“…2. Measured computational workload of a typical H.264 decoding application (video steam "foreman" on an ARM926EJ processor) [11]. (CGRAs), the computation tasks are usually divided into many small kernels (compiled in the forms of multiple contexts) which are then mapped on and executed by the array repeated [14].…”

Section: Algorithm Analysis and Design Considerationmentioning

confidence: 99%

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

Liu

Wang

Zhu

et al. 2015

IEEE Trans. Multimedia

Self Cite

View full text Add to dashboard Cite

A coarse-grained Reconfigurable Processing Unit (RPU) consisting of 16×16 multi-functional Processing Elements (PEs) interconnected by an area-efficient Line-Switched Mesh Connect (LSMC) routing is implemented on a 5.4mm×3.1mm die in TSMC 65 nm LP1P8M CMOS technology. A Hierarchical Configuration Context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two System-on-a-Chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode 1920×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a 14.3× improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode 720×480 H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and a 3.96× improvement on energy efficiency compared with the ADRES reconfigurable processor. IndexTerms-Coarse-grained reconfigurable array, reconfigurable computing, video decoding.

show abstract

“…A heterogeneous platform integrated in a SoC comprising both specialized hardware accelerators and general-purpose processors is therefore a widely accepted solution [7], [8], [19].…”

Section: A Computing Environmentmentioning

confidence: 99%

List Scheduling in Embedded Systems under Memory Constraints

Arras

Fuin

Jeannot

et al. 2013

2013 25th International Symposium on Computer Architecture and High Performance Computing

View full text Add to dashboard Cite

International audienceVideo decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through appropriate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20\% can be achieved. Lastly, we show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics.Le décodage vidéo et le traitement d'image dans les systèmes embarqués sont sujets à de fortes contraintes de ressources, particulièrement en termes de mémoire. Les heuristiques d'ordonnancement de liste à priorités statiques (HEFT, SDC,...) étant les solutions les plus souvent citées en raison à la fois de leurs bonnes performances et de leur faible complexité, nous proposons une méthode visant à y introduire la notion de mémoire. De plus, nous montrons que par le biais d'un ajustement adapté des priorités des tâches et d'un recours judicieux à l'insertion, des accélérations jusqu'à 20% peuvent être obtenues. Enfin, nous montrons que notre technique permet d'empêcher les interblocages et de réduire significativement l'empreinte mémoire requise comparé à des heuristiques d'ordonnancement de liste classiques

show abstract

Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System

Cited by 10 publications

References 14 publications

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

List Scheduling in Embedded Systems under Memory Constraints

Contact Info

Product

Resources

About