An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CG) stage and an admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the cross-term in a two-dimensional Taylor approximation of the () characteristic can cancel the traditionally dominant square-law term in the () relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF 3.5 dB and IIP2 +20 dBm, while simultaneously achieving an IIP3 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and 2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm 2 .

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-An inductorless LNA with active balun is designed for multi-standard radio applications between 100MHz and 6GHz. It exploits a combination of a common gate stage and a common source stage with replica biasing to maximize balanced operation. The NF is designed to be around 3dB by using the noise canceling technique. Its best performance is achieved between 300MHz to 3.5GHz with gain and phase errors below 0.3dB and ±2degrees, 15dB gain, S11<-14dB, IIP3 = 0dBm and IIP2 higher than +20dBm at a total power consumption of 21mW. The circuit is fabricated in a baseline 65nm CMOS process, with an active area of only 0.01mm 2 . The circuit simultaneously achieves impedance matching, noise canceling and a well balanced output.

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Wideband receivers are required for many applications including the upcoming software-defined radio (SDR) architectures and ultra-wideband communication standards [1][2][3]. These standards cover a frequency spectrum from a few hundred MHz up to 6GHz. Co-operability with other communication devices (e.g., cellular and WLAN) operating in the same spectrum is mandatory, setting especially stringent demands on the wideband linearity of such receivers. The use of area-consuming on-chip inductors must be avoided as the cost per area of modern CMOS processes is high. The receiver preferably has a single-ended RF-input, as this avoids the use of an external broadband balun and its accompanying losses. A 65nm CMOS inductor-less wideband LNAmixer topology is presented, merging a current commutating I/Qmixer with a noise canceling balun-LNA. Figure 17.3.1 shows the topology of the proposed receiver frontend, which combines the functionality of a balun, an LNA and an I/Q-Mixer (Blixer) into one circuit cell. The transistor in commongate (CG) configuration gives wideband input matching (Z in ≈1/g m ). The inverter-based common-source (CS) stage produces a current in anti-phase with the CG output current, providing the single-to-differential conversion. The normally dominant thermal noise of the CG stage is canceled robustly [4]. The noise current of the CG transistor generates a noisy input voltage on the source resistance (R S ). This voltage results in an output current in the CS stage which is in-phase and fully correlated with the noise current of the CG transistor. The CG noise can thus be canceled at the differential output. The effective g m of the CS stage is 4 times higher than the CG g m in order to limit its noise contribution. The output currents of the CG and CS stage (g m ·v rf and 4·g m ·v rf in Fig. 17.3.1) are distributed to two identical current-commutating mixer cells, as shown in Fig. 17.3.2. The drains of the transistors commutating the CS current are loaded by only ¼ of the total RC load. The difference in loading compensates the (4×) difference in g m of the CG and CS stage, leading to equal conversion gain of the CG and CS side of the circuit. This gain balancing renders simultaneous canceling of the noise and distortion of the CG transistor, as in the LNA in [5]. However, in contrast to that design, here the canceling takes place at the IF output, after frequency translation. As the distortion of the CG transistor is canceled, the inverter-based CS stage is biased for minimal 2 ndorder distortion to obtain a high IIP2 of the complete circuit. In contrast to narrowband systems 2 nd -order distortion products can fall in-band, thus obtaining a high IIP2 is important for wideband receivers. The Blixer topology has only two internal RF nodes, the drains of the CG and CS transistors. The impedance at these points is set by the input impedance of the mixer devices. This impedance (~1/g m of the mixer transistors) is low, approximately 100Ω and 25Ω for the CG and CS side, respectively. The absence of high ...

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A 24GHz multi-channel integer-N PLL as part of a 24GHz ISM-band wireless sensor network used for wireless commissioning of light sources (>1000) in greenhouses is presented. The PLL supports operation across five channels, each at 1Mb/s of datarate in a FSK modulated system. As power consumption is critical for battery lifetime, the synthesizer exhibits a settling time of around 10µs. The PLL contains of a 24GHz LC-VCO, programmable divider, CMOS digital PFD and loop polarity control. The innovative charge pump circuit combines rail-to-rail output range with high output impedance. The IC occupies 2mm 2 and the power consumption is 21mW from a 1.8/2.5V dual supply voltage.Index Terms -BiCMOS, frequency synthesizer, FSK, multi-channel, 24GHz ISM band, wireless sensor networks.