In this paper we assess gate oxide .thickness (t, J scaling issues with respect to key plasma processes -metal etch, contact etch and deposition, and relate the scaling trends to the mechanism of damage involved. We show that for electron shading effect, the damage effects peak for gate oxide around 30A-40A. We propose an antenna array scheme for plasma damage detection at small antenna ratios. We show that the local substrate potential can have a significant impact on device damage. Channel hot carrier (CHC) stress lifetime for antenna devices (both IiMOSFET and pMOSFET) degrade with 2-lox decrease in lifetime for lox increase in post-plasma stress Ig: Diode protection schemes are shown to be effective for 21A-32A FETs.
In this abstract we present a highly manufacturable, high performance 90nm technology with best in class ,performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uAium and 587uAium are obtained for nMOS and PMOS transistors respectively at I .2V Vdd and an Ioff of 60nMpm. An industry leading 90nm technology CVil of 0 . 6 1~s and 1 .
CMOS technology for 1.2V high performance applications is being scaled to sub-0.09pm physical nominal gate lengths and with effective gate dielectric thickness less than 2nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09pm (post gate reoxidation), and gate dielectric thickness of 2.7nm (nMOS), 3.0nm (PMOS) (inversion at 1.2V), nMOS and PMOS Idrive is 763 pA/pm and 333 pA/pm respectively, at 1.2V with maximum Ioff=5nA/pm. Gate-drain overlap in this work is -2 10 h i d e and bottomwall junction capacitance is reduced to 0.8 fF/pm2 (PMOS) and 1.1 fF/Fm2 (nMOS). With reduced parasitics and high drive current, the 1.2V technology FOM (Figure-of-Merit) is > 39GHz, meeting the roadmap trend.
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