Antenna device reliability for ULSI processing

Abstract

In this paper we assess gate oxide .thickness (t, J scaling issues with respect to key plasma processes -metal etch, contact etch and deposition, and relate the scaling trends to the mechanism of damage involved. We show that for electron shading effect, the damage effects peak for gate oxide around 30A-40A. We propose an antenna array scheme for plasma damage detection at small antenna ratios. We show that the local substrate potential can have a significant impact on device damage. Channel hot carrier (CHC) stress lifetime for antenna devices (both IiMOSFET and pMOSFET) degrade with 2-lox decrease in lifetime for lox increase in post-plasma stress Ig: Diode protection schemes are shown to be effective for 21A-32A FETs.

Behaviors and physical degradation of HfSiON MOSFET linked to strained CESL performance booster

“…As such, HCI lifetime prediction can be misled when the data is garnered then extrapolated from higher stresses. However, such phenomenon is not observed from pMOS due presumably to polarity effect of plasma charging [6]. Since mechanical stress discrepancy between cCESL (-0.3GPa) and tCESL (+0.8GPa) is shallow, it is posited that the effect of mechanical strain on degradation would be negligible especially for channel length larger than 0.1μm [7].…”

MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology

“…A well known, state of the art protection, shown in Fig.1, is a tie down diode from the MOS gate into the well where the MOS transistor resides [1,2,3]. In case that the tie down diode area is large enough in relation to the connected antenna the MOS transistor characteristic will not be affected by PID.…”

A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology

“…PID is well known to degrade both gate dielectric and metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability [2]. The silicon wafer manufacturing employs many plasma-processing steps, including gate electrode etching [3], high density plasma chemical vapor deposition (HDP-CVD) [4], metal interconnect etching [5], and photoresist ashing [6].…”