A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology

High K / Metal Gate of Short-Channel SOI NMOSFET Research

“…Figure 5 shows the output characteristics of L =40nm TaCN/La 2 O 3 gate structure compares with traditional gate structure, both in linear region and in saturation region, the traditional gate structure drive current larger than TaCN/La 2 O 3 gate structure drive current, because high-k gate dielectric compares with SiO 2 gate dielectric, the former inverse layer carrier mobility significantly lower than the latter, the soft-phonon scattering of high-k gate dielectric is one of the main mobility degradation mechanisms, because metal atoms and oxygen atoms with low bond strength (much lower than Si-O bond in SiO 2 ), cause the soft phonon scattering enhancement and channel carrier mobility degeneration, this is the high-k dielectric (including La 2 O 3 ) inherent [7] , according to linear region current equation:…”

Fabrication Technique for pMOSFET poly-Si/TaN/TiN/HfSiAlON Gate Stack

“…Over the past ten years, the integration of Hf-based high-k dielectrics, such as HfO 2 and HfSiON, and metal gate electrode materials, such as TaN, TiN, and TaSiN, have been widely studied for nanoscale CMOS devices. [1][2][3][4] Among the many high-k and metal gate integration issues, their patterning presents a critical challenge due to the low volatility of the halogendies of these new materials, which makes it difficult to achieve all required specifications such as a near vertical sidewall profile, low critical dimension (CD) gain, and high selectivity. 5,6 Meanwhile, in order to avoid these difficulties when etching thick metal gates, one popular approach is to use a gate stack with a thin metal layer inserted between a high-k dielectric and poly-Si, forming a metal inserted poly-Si stack (MIPS) structure.…”