The flow characteristics of a number of underfills were evaluated with quartz dies of different patterns and pitches bonded on different substrate surfaces. Perimeter, mixed array, and full array patterns were tested. Observations on the flow front uniformity, streaking, voiding, and filler segregation were collected. The information was compared with the results predicted by a new simulation code, plastic integrated circuit encapsulationcomputer aided design (PLICE-CAD) under DARPA-funded development. The two-phase model of the combined resin and air takes into account geometrical factors such as bumps and die edges, together with boundary conditions in order to track accurately the propagation of the flow fronts. The two-phase flow field is based on the volume-of-fluid (VOF) methodology embedded in a general-purpose three-dimensional (3-D) flow solver. Index Terms-Capillary flow, filler settling, flip chip, flow simulation, flow streaking, full array pattern, mixed array pattern, organic laminates, peripheral pattern, quartz dies, underfill flow.
As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-m area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 m diameter and lines and spaces of 25 m. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for microvia wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 m and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.Index Terms-Conductors, embedded passives, fine lines, global interconnect, high speed, low-loss dielectrics, microvia, PWB, stacked vias, system-in-a-package (SIP), system-on-a-package (SOP), thin film.
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