Next-Generation Microvia and Global Wiring Technologies for SOP

Abstract

As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-m area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 m diameter and lines and spaces of 25 m. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for microvia wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 m and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.Index Terms-Conductors, embedded passives, fine lines, global interconnect, high speed, low-loss dielectrics, microvia, PWB, stacked vias, system-in-a-package (SIP), system-on-a-package (SOP), thin film.

Filling mechanism in microvia metallization by copper electroplating

“…Microvia filling by copper electroplating has been an important process technology in the fabrication of high density interconnections (HDI) of printed circuit boards (PCBs) and IC packaging substrates [1][2][3][4][5][6][7][8][9]. The progress mode of copper electrodeposition in the microvia must be bottom-up in order to ensure a void-free filling.…”

Superconformal Filling of Through Vias in Glass Interposers

“…2 Recently, glass interposers (GIs) have been attracting increased interest because of their lower cost and certain performance advantages. [3][4][5][6][7] Due to its lower thermal conductivity compared to Si, it is even more important to fill holes in glass with Cu to improve heat dissipation, and it would be desirable to do so by less cumbersome means than used for TSVs. W.P.…”

The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade

“…The recently released 2003 ITRS roadmap [15] calls for package signal speeds and flip chip pad pitch to satisfy 50 nm node requirements for future ICs. There have been significant developments in microvia and high-density build-up substrates and the state-of-the-art manufacturing processes use line and space technology and 50-75 microvias [16]- [20]. Several low loss and low k polymers including epoxy, A-PPE, Avatrel, BCB, polyimide, and LCP have been evaluated at the PRC for signal speed and loss at frequencies up to 20 GHz.…”

“…Embedded high-k polymer/ceramic nanocomposite capacitors (dielectric constant [15][16][17][18][19][20] have been used primarily for the decoupling applications as discussed earlier. Currently, a capacitance density has been reported with a thin film of using hydrothermal synthesis [37] that can be integrated with the SOP.…”