Conventional High Intensity Focused Ultrasound (HIFU) is a therapeutic modality which is extracorporeally administered. In applications where a relatively small HIFU lesion is required, an intravascular HIFU probe can be deployed to the ablation site. In this paper, we demonstrate the design and implementation a fully integrated HIFU drive system on a chip to be placed on a 6 Fr catheter probe. An 8-element capacitive micromachined ultrasound transducer (CMUT) ring array of 2 mm diameter has been used as the ultrasound source. The driver chip is fabricated in 0.35 μm AMS high-voltage CMOS technology and comprises eight continuous-wave (CW) high-voltage CMUT drivers (10.9 ns and 9.4 ns rise and fall times at 20 V output into a 15 pF), an eight-channel digital beamformer (8-12 MHz output frequency with 11.25 phase accuracy) and a phase locked loop with an integrated VCO as a tunable clock source (128-192 MHz). The chip occupies 1.85 × 1.8 mm area including input and output (I/O) pads. When the transducer array is immersed in sunflower oil and driven by the IC with eight 20 V CW pulses at 10 MHz, real-time thermal images of the HIFU beam indicate that the focal temperature rises by 16.8 C in 11 seconds. Each HV driver consumes around 67 mW of power when driving the CMUT array at 10 MHz, which adds up to 560 mW for the whole chip. FEM based analysis reveals that the outer surface temperature of the catheter is expected to remain below the 42C tissue damage limit during therapy.
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High Intensity Focused Ultrasound (HIFU) is generally administered externally, or through body orifices such as the esophagus, the urethra, the uterus, or the rectum. The devices used in conventional treatment are not suitable to be used in endoscopic interventions or in intravascular catheterization due to their dimensions. This paper presents the design of a drive integrated circuit for driving a CMUT therapy array of 2 mm diameter such that whole device fit through key holes in endoscopic treatment or through vessels. The proposed ASIC is composed of (1) an 8 channel drive signal generator, (2) 8 high voltage drivers, and (3) a PLL for the local generation of a high frequency tunable master clock signal based on a low frequency reference. All designs are in austriamicrosystems h35 HighVoltage CMOS technology with 1.3×3 mm 2 die area including ESD protection pads.
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