2017
DOI: 10.1109/jsen.2017.2704623
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Fabrication of High-Efficiency CMUTs With Reduced Parasitics Using Embedded Metallic Layers

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Cited by 6 publications
(2 citation statements)
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“…Another approach to reduce the CMUT parasitic capacitance is using embedded patterned BE layers to minimize the overlap between top and bottom electrodes [13,14]. Using embedded electrode method to make topography-free surfaces adds an extra etching step, significantly increasing the roughness of the dielectric surface due to etching.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…Another approach to reduce the CMUT parasitic capacitance is using embedded patterned BE layers to minimize the overlap between top and bottom electrodes [13,14]. Using embedded electrode method to make topography-free surfaces adds an extra etching step, significantly increasing the roughness of the dielectric surface due to etching.…”
Section: Introductionmentioning
confidence: 99%
“…Cavity edge insulator extension method has been recently proposed in [15] to increase the reliability in CMUT cells for high ultrasound power transmission application. Although it significantly increases the breakdown voltage and CMUT's lifetime, using the sandwich method like [14], increases the effective gap resulting in degrading device performance. Besides, this approach adds an extra etching step and also height difference over the edges of the membranes-since the new PE-SiO 2 layer exclusively stays on the edge of the membranes-that makes the following deposition/patterning processes difficult.…”
Section: Introductionmentioning
confidence: 99%