2018
DOI: 10.1088/1361-6439/aabe0c
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Low temperature CMUT fabrication process with dielectric lift-off membrane support for improved reliability

Abstract: This paper reports an improved CMOS compatible low temperature sacrificial layer fabrication process for Capacitive Micromachined Ultrasonic Transducers (CMUTs). The process adds the fabrication step of silicon oxide evaporation which is followed by a lift-off step to define the membrane support area without a need for an extra mask. This simple addition improves reliability by reducing the electric field between the top and bottom electrodes everywhere except the moving membrane without affecting the vacuum g… Show more

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Cited by 11 publications
(7 citation statements)
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References 29 publications
(47 reference statements)
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“…Therefore, in order to qualitatively validate the ECR approach, it is considered that the mechanical energy output for a CMUT is proportional to the acoustic intensity, which can be measured through pressure in the far field [ 20 ]. For this purpose, a 4 membrane CMUT element is fabricated [ 21 ] as part of an array using the parameters of Table 2 as shown in Figure 11 . Then, pressure measurements in a water tank are performed and compared with model predictions for both AC only and DC biased operation.…”
Section: Experimental Validation Of Mechanical Energy Outputmentioning
confidence: 99%
“…Therefore, in order to qualitatively validate the ECR approach, it is considered that the mechanical energy output for a CMUT is proportional to the acoustic intensity, which can be measured through pressure in the far field [ 20 ]. For this purpose, a 4 membrane CMUT element is fabricated [ 21 ] as part of an array using the parameters of Table 2 as shown in Figure 11 . Then, pressure measurements in a water tank are performed and compared with model predictions for both AC only and DC biased operation.…”
Section: Experimental Validation Of Mechanical Energy Outputmentioning
confidence: 99%
“…The CMUT arrays are fabricated using low-temperature CMUT-on-CMOS process [2], [13]. The arrays are processed on the CMOS substrate which is passivated with 3 m of Plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN).…”
Section: Cmut Design and Fabricationmentioning
confidence: 99%
“…Many solutions to dielectric charging have been suggested, including optimization of film surface roughness [19] and quality [20], investigation of different dielectrics [15], [21], and architectural adjustments such as isolation posts [8], [22], [23]. However, optimization of films alone does not fully eliminate charging.…”
Section: Introductionmentioning
confidence: 99%