A three-course sequence of cross-disciplinary real-time and embedded systems courses has been introduced at RIT • . We are teaching these courses in a studio-lab environment teaming computer engineering and software engineering students. The courses introduce students to programming both microcontrollers and more sophisticated targets, use of a commercial real-time operating system and development environment, modeling and performance engineering of these systems, and their interactions with physical systems.
With the immense size of images, compression has become a common way of minimizing the amount of storage necessary for images. This is also beneficial for transmission purposes. The Joint Photographic Experts Group (JPEG) standard is frequently used for still images. This standard is very flexible and many of the same algorithms can be used for video applications. Video applications require large amounts of data to be processed every second. Therefore, the following describes the hardware design of a chip allowing for high-speed compression. The design uses the JPEG algorithms and is targeted towards ASIC design. Further pians include use of field programmable gate arrays (FPGAs). The hardware design is based on grayscale images and only works with the raw image data.
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