A novel GPU-based simulation of spiking neural networks is implemented as a hybrid system using ParkerSochacki numerical integration method with adaptive order. Full single-precision floating-point accuracy for all model variables is achieved. The implementation is validated with exact matching of all neuron potential traces from GPU-based simulation versus those of a reference CPU-based simulation. A network of 4096 Izhikevich neurons simulated on an NVIDIA GTX260 device achieves real-time performance with a speedup of 9 compared to simulation executed on Opteron 285, 2.6-GHz device.Index Terms-GPU, CUDA, STDP, spiking neural network, high accuracy, parallel computing, shared memory.

We present a novel parallel programming model called Cluster-M. This model facilitates the e cient design of highly parallel portable software. The two main components of this model are Cluster-M Speci cations and Cluster-M Representations. A Cluster-M Speci cation consists of a number of clustering levels emphasizing computation and communication requirements of a parallel solution to a given problem. A Cluster-M Representation on the other hand, represents a multi-layered partitioning of a system graph corresponding to the topology of the target architecture. An algorithm for generating Cluster-M Representations is given. A set of basic constructs essential for writing Cluster-M Speci cations using PCN are presented in this paper. Cluster-M Speci cations are mapped onto the Representation using a proposed mapping methodology. Using Cluster-M a single software can be ported among various parallel computing systems.

The MATMOS Fourier Transform Infrared (FTIR) spectrometer is one of three scientific instruments on the previously proposed MARVEL mission. MATMOS requires computationally intensive floating-point signal processing to reduce the amount of data prior to downlink. With the goal of reducing design time and the size and weight of instrument electronics, this paper presents an FTIR spectrometry implementation targeting the Xilinx Virtex-4FX hybrid-FPGA and its embedded PowerPC 405 processor. We explore different hardware and software optimizations and architectural configurations of the hybrid-FPGA system to demonstrate optimal performance in onboard data processing. By including a dedicated floatingpoint unit and dot-product co-processor in the hardware as well as utilizing optimized single-precision math library functions and a modified IBM PowerPC performance library in the software, we demonstrate a more than 8x reduction in execution time compared to the non-optimized software only implementation. A dual-processor design concept as an enhancement that would further reduce the execution time is also presented. 1 2 3

With the immense size of images, compression has become a common way of minimizing the amount of storage necessary for images. This is also beneficial for transmission purposes. The Joint Photographic Experts Group (JPEG) standard is frequently used for still images. This standard is very flexible and many of the same algorithms can be used for video applications. Video applications require large amounts of data to be processed every second. Therefore, the following describes the hardware design of a chip allowing for high-speed compression. The design uses the JPEG algorithms and is targeted towards ASIC design. Further pians include use of field programmable gate arrays (FPGAs). The hardware design is based on grayscale images and only works with the raw image data.

Unit of frequency measure based on critical bandwidth Coder/decoderprovides 16 bit samples of analog signal Discrete Cosine Transform Difference between two frequencies in barks. Finite Impulse Responsefilter based on the weighted sum of input values. Fast Fourier Transformtime to frequency transform Subbands that are less than the bound are coded in stereo, while 1 the sum of the two channels is coded for the higher subbands. Interrupt Service Routinecode executed to service an interrupt Kilo bits per second Least Significant Bytelower 8 bits of a 16 bit value The science of how the ear and brain perceive sounds. The effect of one tone or noise to make a test tone inaudible or less loud. The SPL of the surrounding frequencies that is masked out by the masking frequency Million Instructions Per Second Mask to Noise Ratio Moving Pictures Experts Group Most Significant Byteupper 8 bits of a 16 bit value Encoding of stereo signals as their sum and difference Noise like frequency components Personal Computer Pulse Code Modulation Continuous represented as discrete values.