<title>Real-time implementation of JPEG encoder/decoder</title>

Abstract

With the immense size of images, compression has become a common way of minimizing the amount of storage necessary for images. This is also beneficial for transmission purposes. The Joint Photographic Experts Group (JPEG) standard is frequently used for still images. This standard is very flexible and many of the same algorithms can be used for video applications. Video applications require large amounts of data to be processed every second. Therefore, the following describes the hardware design of a chip allowing for high-speed compression. The design uses the JPEG algorithms and is targeted towards ASIC design. Further pians include use of field programmable gate arrays (FPGAs). The hardware design is based on grayscale images and only works with the raw image data.

Field Programmable Gate Array Applications—A Scientometric Review

“…These kind of applications have been used for different systems such as the Mars rovers computer vision [669,670], autonomous vehicles vision [1624][1625][1626][1627][1628][1629], atmospheric turbulence mitigation for telescope pictures reconstruction [723,724], among others. In addition, we found image and video compression standards implemented in FPGAs, from JPEG [1630], to most recent video compression standard H.265 [593]. The implementation in FPGAs of the different blocks that integrate the compression standards or codecs (intra prediction [1631][1632][1633], Context-adaptive binary arithmetic coding (CABAC) [783,1634], DCT [775,1635], Context-adaptive variable-length coding (CAVLC) [1636][1637][1638], etc.)…”