The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. At the end of the flow, the implementation code is generated automatically from the high-level models. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering.
The watermarking technique is an active subject in current research used as a solution for copyright protection in multimedia documents. In this paper, we propose the first hardware invisible robust video watermarking application based on motion estimation. Since the designers of this application face many challenges, two types of architecture are performed: static and dynamic/partial reconfigurable architecture. The proposed architecture is adapted to HEVC encoded video. Two protection techniques are linked up: the digital watermarking to insert a watermark in the video, and the scrambling technique for overall video protection. The watermark embedding is treated in the horizontal and vertical components of even motion vectors. Eventually, the entire vectors are scrambled. The used watermark is a binary sequence where only one bit is inserted into the horizontal and the vertical components of motion vectors. The recommended architecture applies for slow and fast video sequence, where we use a motion estimator reconfigured according to the macro-block video movement. We also utilize a pipeline structure and a clock gating module to increase computing power and reduce power consumption. Experimental results show that the suggested static and dynamic/partial reconfigurable architecture guarantees material efficiency and superior performance in terms of frequency and power consumption.
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