Networks on Chip (NoCs) can improve a set of performances criteria, in complex SoCs, such as scalability, flexibility and adaptability. However, performances of a NoC are closely related to its topology. The diameter and average distance represent an important factor in term of performances and implementation. The proposed diagonal mesh topology is designed to offer a good tradeoff between hardware cost and theoretical quality of service (QoS). It can contain a large number of nodes without changing the maximum diameter which is equal to 2. In this paper, we present a new router architecture called FeRoNoC (Flexible, extensible Router NoC) and its Register Transfer Level (RTL) hardware implementation for the diagonal mesh topology. The architecture of our NoC is based on a flexible and extensible router which consists of a packet switching technique and deterministic routing algorithm. Effectiveness and performances of the proposed topology have been shown using a virtex5 FPGA implementation. A comparative performances study of the proposed NoC architecture with others topology is performed.
The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. At the end of the flow, the implementation code is generated automatically from the high-level models. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering.
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