Using thin film transistors in active-matrixed addressed large area displays has recently become important in display development. Specifically, a PLZT ceramic dot-matrix display requires high voltage TFT pixel switching. To meet the need, a process has been developed utilizing polysilicon and temperatures less than 850~ which yields MOSFET's capable of operating at voltages in excess of 50V with high ID(o,,/IDr ratios. High mobilities are obtained by fabricating n-channel, accumulation-mode devices in silicon deposited in the amorphous state and later annealed to the final polycrystalline condition.Interest has been growing in the use of thin film transistors for addressing active dot-matrix displays. Although several materials have been investigated, polysilicon offers such advantages as the use of conventional silicon processing techniques and an easy fabrication process (1). High quality devices could also be used as driver circuitry fabricated on the display substrate.PLZT ceramic material has been used in optical shutter applications for several years. Recently, it has been applied to display devices (2). However, for use as a substrate in dot-matrix applications, several constraints are placed on the process for fabrication of the thin film transistors. Most of the wet cleaning schemes presently used in MOS processing severely degrade the PLZT surface, reducing its electro-optic effect. Also, thermal stress due to temperature gradients produces breakage at temperatures as low as 150~ High temperatures (over 200~ can alter the PLZT composition with time, changing its electro-optic effect especially, whenever hydrogen is available in the processing atmosphere or in a deposited film. The lead component is easily reduced by hydrogen, rendering the substrate useless. In addition to these material effects are the requirements that the thin film transistors have low leakage currents in the off state with a high source-to-drain voltage and be able to provide sufficient charging current to charge the capacitive load of the pixel during the short time allotted. Also note that the device must be symmetric.Adhering to the constraints of the PLZT substrate, a process has been developed, utilizing deposited oxide encapsulation, suitable for the production of acceptable thin film transistors, which can be used for pixel switching and driver circuitry. A fully populated PLZT dot-matrix display has been fabricated (3). With slight modifications, the process could be valuable in the formation of stacked transistors utilized in MOS DRAM fabrication. TFT ProcessThe fabrication process for buildin~ n-channel MOSFET's in polysilicon is as follows. 2500A of low temperature oxide (LTO) is deposited by LPCVD (on PLZT) at the temperature of 420~ This is followed by the deposition of silicon using LPCVD at 580~ to a thickness of 5000A. Next, the polysilicon islands for TFT fabrication are defined using normal photolithography techniques, and this step is immediately followed by defining regions for source-drain implant utilizing pho...
Fabrication of SiGe heterojunction bipolar transistors (HBTs) requires a low thermal budget to avoid relaxation of the strained SiGe base layer. Ion implantation is one of the most widely used techniques to achieve contacts. However, due to thermal budget constraints, low temperature rapid thermal annealing (RTA) cycles to activate these implants are insufficient to anneal out all of the implant damage. Polysilicon contacts provide an alternative to ion implantation, but are typically annealed at high temperatures (>950°C) to achieve low sheet resistivity. In this study, amorphous silicon and polycrystalline silicon films were implanted with boron, arsenic, or phosphorus and RTA'd at temperatures from 800°C to 950°C and compared to single crystal silicon with identical implants and RTA cycles. The films were characterized using four-point probe, Hall measurements, TEM (transmission electron microscopy), and SIMS (secondary-ion mass-spectrometry). TEM analysis shows that the amorphous deposition produces larger grains upon RTA due to more rapid grain growth than the polycrystalline deposition. The sheet resistance for the amorphous deposited films is much lower than that of the polycrystalline deposition for all implant conditions. Activations of the implants indicate that the arsenic and phosphorus segregate to the grain boundaries, while the boron does not. The segregation is more significant for the polycrystalline films than for the amorphous films and can be explained by the grain boundary area. For contacts to the SiGe HBT, which requires a low thermal budget, an amorphous deposited silicon film is advantageous over a polycrystalline film at low annealing temperatures because it has lower sheet resistance, less segregation to the grain boundaries, and produces larger grains.
In this study, amorphous silicon and polycrystalline silicon films were implanted with arsenic and subjected to varied low temperature (<900°C) anneal conditions and characterized using TEM. The microstructure is of interest for later correlation with electrical measurements. The amorphous deposition produces larger, more irregular grains with more strain than does the polysilicon deposition for a single-step rapid thermal anneal (RTA) cycle. This can be explained by the number of critical nucleii and the rate of grain growth. The sheet resistivity, as measured by four-point probe, correlates to the deposition conditions. A two-stage anneal makes the grains less irregular by reducing the roughness of the grains and decreasing the strain in the grains. For a given deposition condition, the final microstructure is most strongly influenced by the first anneal. The second anneal produces no clear change in grain size. 800°C anneals result in larger grains than 900°C anneals. This is explained by the presence of less critical nucleii for 800°C anneals. In comparing short and long durations of RTA, the short duration produced slightly larger grains than the long duration RTA due to greater nucleation in the longer RTA wafers. In the case of RTA versus furnace anneals, RTA produces larger, more irregular grains, with more strain in the grains. A model in terms of the size of critical nucleii is used to explain the difference.
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