Fabrication of High Voltage Polysilicon TFT's on an Insulator

Abstract

Using thin film transistors in active-matrixed addressed large area displays has recently become important in display development. Specifically, a PLZT ceramic dot-matrix display requires high voltage TFT pixel switching. To meet the need, a process has been developed utilizing polysilicon and temperatures less than 850~ which yields MOSFET's capable of operating at voltages in excess of 50V with high ID(o,,/IDr ratios. High mobilities are obtained by fabricating n-channel, accumulation-mode devices in silicon deposited in the amorphous state and later annealed to the final polycrystalline condition.Interest has been growing in the use of thin film transistors for addressing active dot-matrix displays. Although several materials have been investigated, polysilicon offers such advantages as the use of conventional silicon processing techniques and an easy fabrication process (1). High quality devices could also be used as driver circuitry fabricated on the display substrate.PLZT ceramic material has been used in optical shutter applications for several years. Recently, it has been applied to display devices (2). However, for use as a substrate in dot-matrix applications, several constraints are placed on the process for fabrication of the thin film transistors. Most of the wet cleaning schemes presently used in MOS processing severely degrade the PLZT surface, reducing its electro-optic effect. Also, thermal stress due to temperature gradients produces breakage at temperatures as low as 150~ High temperatures (over 200~ can alter the PLZT composition with time, changing its electro-optic effect especially, whenever hydrogen is available in the processing atmosphere or in a deposited film. The lead component is easily reduced by hydrogen, rendering the substrate useless. In addition to these material effects are the requirements that the thin film transistors have low leakage currents in the off state with a high source-to-drain voltage and be able to provide sufficient charging current to charge the capacitive load of the pixel during the short time allotted. Also note that the device must be symmetric.Adhering to the constraints of the PLZT substrate, a process has been developed, utilizing deposited oxide encapsulation, suitable for the production of acceptable thin film transistors, which can be used for pixel switching and driver circuitry. A fully populated PLZT dot-matrix display has been fabricated (3). With slight modifications, the process could be valuable in the formation of stacked transistors utilized in MOS DRAM fabrication. TFT ProcessThe fabrication process for buildin~ n-channel MOSFET's in polysilicon is as follows. 2500A of low temperature oxide (LTO) is deposited by LPCVD (on PLZT) at the temperature of 420~ This is followed by the deposition of silicon using LPCVD at 580~ to a thickness of 5000A. Next, the polysilicon islands for TFT fabrication are defined using normal photolithography techniques, and this step is immediately followed by defining regions for source-drain implant utilizing pho...

3-D high-voltage CMOS ICs by recrystallized SOI merged with bulk control-unit

“…In addition to the ease of complete device isolation, SO1 has many inherent advantages such as simple fabrication process, small parasitic capacitance, latch-up free, high-speed, and highpacking density. In fact, several approaches have been made to realize high-voltage devices by utilizing SO1 structures such as SOS (11, SIMOX (2),and polysilicon TFT (3)as well as laser recrystallized SO1 (4,5).However, a conplete monolithic integration of SO1 high-power output circuits and low-voltage bulk CMOS control units has not been reported yet.…”