SummaryDue to the increasing demands for more power in data intensive computing, low power design methodologies play a very important role in these systems. For noncritical data, the approximate computing that significantly reduces the power can be used. In this paper, an approximate floating‐point adder is proposed by designing an inexact mantissa adder and exponent subtractor. The results indicate that the power consumption and delay of the proposed approximate floating‐point adder have been decreased by 37% and 62% compared with the IEEE‐754 single‐precision floating‐point (FP) adder. Furthermore, compared with a state‐of‐the‐art inexact floating‐point adder, the proposed method provides an improvement of 7% and 21% in terms of the power consumption and delay. In addition, the proposed floating‐point adder has been investigated in terms of error, and the mean error of the proposed floating‐point adder at worst is about 55% less than that of another approximate floating‐point adder considered in this work. High dynamic range (HDR) images are processed using the proposed approximate floating‐point adders to show the performance of the proposed adder. The results show that, on average, peak signal‐to‐noise ratio increased by 9.6 and 18.64 dB, which may be achieved by utilizing the proposed floating‐point adder.
Due to technology scaling, reliability has become one of the biggest challenges in VLSI circuits. A number of techniques have been introduced in the literature, especially for arithmetic and logic unit in computers. One of well-known schemes for fault-tolerant arithmetic is the use of arithmetic residue codes. A key problem with most of the previous works regarding residue-based checker is that these methods impose an unacceptable area penalty. In this paper, we propose a novel residue checker with current mode multi-valued logic (CMMVL). A plain design procedure with arbitrary modulo is introduced; also a more efficient integrated scheme for modulo 3 has been demonstrated. The results of the plain CMMVL scheme showed up to 19.5% and 42.9% lower delay and power consumption, respectively, compared with those of the conventional CMOS. Also, utilizing the integrated CMMVL provided, on average, about 17.7% and 80.2% lower delay and power consumption, respectively.
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