On the Design of Iterative Approximate Floating-Point Multipliers

Towhidy, Ahmad; Omidi, Reza; Mohammadi, Karim

doi:10.1109/tc.2022.3216465

Cited by 8 publications

(2 citation statements)

References 40 publications

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“…The work [16] proposes the floating-point approximate PAM multiplier with run-time customisation, which can successfully replace a full-precision floating-point multiplier in some deep neural networks and image-processing applications. In [17], the authors proposed an iterative approximate floating-point multiplier based on two-dimensional pseudo-Booth encoding. The accuracy of the proposed multiplier is tuned by three parameters: iteration, encoder's radix, and word length after truncation.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier

Pilipović¹,

Bulić²,

Lotrič³

2023

Preprint

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<p>This paper proposes a novel approximate bfloat16 multiplier with on-the-fly adjustable accuracy for energy-efficient learning in deep neural networks. The size of the proposed multiplier is only 62% of the size of the exact bfloat16 multiplier. Furthermore, its energy footprint is up to five times smaller than the footprint of the exact bfloat multiplier. We demonstrate the advantages of the proposed multiplier in deep neural network learning, where we successfully train the ResNet-20 network on the CIFAR-10 dataset from scratch. </p>

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Section: Introductionmentioning

confidence: 99%

Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier

Pilipović¹,

Bulić²,

Lotrič³

2023

Preprint

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“…Floating point (FP) multiplication is an essential component required in a large set of FPGA based hardware acceleration application [2]. So, efficient implementation of FPGA based floating point multipliers are highly desirable.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

et al. 2023

IJFMR

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: Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. This paper presents, Design and Implementation of FPGA based Complex Floating Point Multiplier using Combined Integer and Floating point Multiplier (CIFM). The Processing speed of the multipliers decides the execution time of the system as it consumes most of the time. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The architectures for the three multiplier solutions of complex multiplier for 32 x 32 bit complex numbers multiplication are coded in VHDL and implemented through Xilinx ISE 13.4 navigator and Modelsim 5.6 and their performance is compared. The complex floating point multiplication with single precision using CIFM multiplier has comparatively less amount of delay and power consumption with respect to Vedic and Array multiplier.

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Design of Approximate Tree Multiplier Using Approximate Compressor for Image Processing Applications

Venkatnarayanan,

Somasundaram

2024

IETE Journal of Research

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On the Design of Iterative Approximate Floating-Point Multipliers

Cited by 8 publications

References 40 publications

Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier

Energy-efficient neural network learning with accuracy-adjustable floating-point multiplier

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

Design of Approximate Tree Multiplier Using Approximate Compressor for Image Processing Applications

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