Design of low power approximate floating‐point adders

Abstract

SummaryDue to the increasing demands for more power in data intensive computing, low power design methodologies play a very important role in these systems. For noncritical data, the approximate computing that significantly reduces the power can be used. In this paper, an approximate floating‐point adder is proposed by designing an inexact mantissa adder and exponent subtractor. The results indicate that the power consumption and delay of the proposed approximate floating‐point adder have been decreased by 37% and 62% compared with the IEEE‐754 single‐precision floating‐point (FP) adder. Furthermore, compared with a state‐of‐the‐art inexact floating‐point adder, the proposed method provides an improvement of 7% and 21% in terms of the power consumption and delay. In addition, the proposed floating‐point adder has been investigated in terms of error, and the mean error of the proposed floating‐point adder at worst is about 55% less than that of another approximate floating‐point adder considered in this work. High dynamic range (HDR) images are processed using the proposed approximate floating‐point adders to show the performance of the proposed adder. The results show that, on average, peak signal‐to‐noise ratio increased by 9.6 and 18.64 dB, which may be achieved by utilizing the proposed floating‐point adder.

Metrics, Noise Propagation Models, and Design Framework for Floating-Point Approximate Computing

“…The CFPU in [28] avoided the multiplication by finding and discarding one mantissa and directly using the other one. A fixed-point adder called reconfigurable approximate carry look-ahead adder (RAP-CLA) was used in [29] to design an approximate floatingpoint adder. Compared with the existing advanced floatingpoint adder, its power consumption and delay are increased by 7% and 21% respectively.…”

“…The corresponding CN (app) can be obtained through (27). Combining the requirement and the CN (app) with the metrics defined in (29), the corresponding efficient bit width of mantissa, w, can be achieved. Thus, three key factors(approximation schemes, circuit topology and the efficient bit width of mantissa) of circuit design have been obtained, as shown in Fig.…”

“…Once CN (app) is obtained, combined with the efficient bit width of mantissa, the noise distribution will be easily got. Further, the quality of data can be estimated through (29) or other metrics, Q in Fig. 5.…”

“…the quality of the data generated by the application could be evaluated. The specific efficient bit width could be obtained by combining users' requirements with (29).…”

Highly accurate division and square root circuits by exploiting signal correlation in stochastic computing

“…SC belongs to approximate computing paradigm which can reduce the hardware cost of the circuit. 5,6 Converting real numbers into SNs requires stochastic number generators (SNGs). Generally, an SNG consists of two components, a random number generator (RNG) and a comparator (CMP).…”