This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix‐2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field‐programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10‐s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high‐speed application in microprocessor environment.
Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.
For implementation of a fast arithmetic algorithm and efficient hardware realization, signed digit representation is crucial. Redundant binary (RB) and 2's complement number representation is the most widely used technique for representation signed digit number. The drawbacks of RB technique include multi valued logic as well as need of unconventional hardware blocks. Though 2's complement notation is efficient and commonly applicable, it needs further optimization in terms of delay and area. In this paper we proposed binary arithmetic operation using inverted encoding of negabits (IEN), where arithmetic value -1 (0) is represented for 0 (1). The proposed IEN adder is simulated using ISim simulator and synthesized using xc4vlx15-12sf363 FPGA device. The proposed work is verified in terms of utilizing the same hardware blocks as that of conventional signed digit representations. The use of IEN representation advances the signed value in comparison with 2's complement number representation.
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