Time efficient signed Vedic multiplier using redundant binary representation

Fast signed multiplier using Vedic Nikhilam algorithm

“…Similarly, Table 3 depicts delay comparison of the proposed design in Spartan‐3 device with Array multiplier, Wallace tree multiplier, Booth multiplier, and various multipliers reported in [10, 11, 16]. The16 × 16 proposed design have almost 54, 56, 46, 47, 38 and 34% of less delay over Array multiplier [10], Wallace tree multiplier [10], Booth multiplier [10], and various Vedic multiplier reported in [10, 11, 16], respectively.…”

“…Table 4 shows the comparison of device utilisation (four input LUTs) of the proposed structure as compared to Booth multiplier and signed Vedic multiplier reported in [3, 16]. This design implementation is also area efficient.…”

“…Recently, different decimal Vedic algorithms have been explored to in binary platform [3]. A large amount of work on multiplier, divider, squaring and cube architectures has been published in [3][4][5][6][7][8][9][10][11][12][13][14][15][16]. The controversies with the book 'Vedic Mathematics' is normally related to the word 'Vedic' and its origin.…”

“…The proposed multiplier requires fewer cycles as it deals with more than 1-bit of both multiplicand and multiplier in each cycle. This motivated us to extend our prior work in [5,16] and design a newly signed binary multiplier using Nikhilam sutra and associated hardware implementation. We hope that the proposed architecture may be useful for future research for signed operand multiplication.…”

Pipelined vedic multiplier with manifold adder complexity levels

“…The 'Vertical and Crosswise' technique followed by UT Sutra is as shown in Figure 2. The bits of the input numbers are multiplied vertically and also in a crosswise manner in different steps and the concatenation of the partial products obtained in these individual steps lead to the output of the multipliers [18]. It can be observed that the UT Sutra supports pipelining and this method is followed for the faster output generation of the multipliers [19][20][21].…”