Efficient ASIC and FPGA implementation of cube architecture

Abstract

This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix‐2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field‐programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10‐s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high‐speed application in microprocessor environment.

Fast signed multiplier using Vedic Nikhilam algorithm

“…In recent years, in addition to high‐speed multiplier [5], our works on the novel square and cube structure are reported in [8, 9]. These designs reduce the square or cube of a large order operand into a smaller order operand with some arithmetic operation.…”

“…These designs reduce the square or cube of a large order operand into a smaller order operand with some arithmetic operation. In these works, the author in [8, 9] have extended decimal algorithm to binary number system. Based on Urdhva Tiryagbhyam sutra, authors in [10] reported a fast 16 × 16 bits Vedic multiplier utilising compressor adders.…”

Time efficient signed Vedic multiplier using redundant binary representation

“…The larger calculation is reduced to a smaller calculation by using the algorithms of Vedic mathematics [7]. Many significant amount of works has been published using the concept of Vedic mathematics, obtaining efficient multiplier, divider, squaring and cube architectures [8–19]. The controversies regarding the book ‘Vedic mathematics’ is mainly associated to the term ‘Vedic’ and its origin.…”

“…In recent time, apart from multiplier architecture [10], we have worked on dedicated and efficient square and cube architectures using algorithms of Vedic mathematics [13, 14]. These proposed designs convert the square or cube of a large magnitude number into a smaller magnitude number along with some arithmetic operation.…”

“…These proposed designs convert the square or cube of a large magnitude number into a smaller magnitude number along with some arithmetic operation. In both of the works [13, 14] decimal algorithm is successfully extended to binary radix‐2 number system considering digital platforms. Again, the design performances of these square and cube architectures are found better as compared with various state‐of‐the‐art conventional and Vedic architectures.…”