Articles you may be interested inLow-voltage transparent electric-double-layer ZnO-based thin-film transistors for portable transparent electronics Appl. Phys. Lett. 96, 043114 (2010); 10.1063/1.3294325 ZnO-based nonvolatile memory thin-film transistors with polymer dielectric/ferroelectric double gate insulators Appl. Phys. Lett. 90, 253504 (2007); 10.1063/1.2749841 ZnO-based thin-film transistors of optimal device performance
Transparent thin-film transistors (TTFTs) with an amorphous zinc tin oxide channel layer formed via rf magnetron sputter deposition are demonstrated. Field-effect mobilities of 5-15 and 20-50 cm 2 V −1 s −1 are obtained for devices post-deposition annealed at 300 and 600°C, respectively. TTFTs processed at 300 and 600°C yield devices with turn-on voltage of 0-15 and −5-5 V, respectively. Under both processing conditions, a drain current onto off ratio greater than 10 7 is obtained. Zinc tin oxide is one example of a new class of high performance TTFT channel materials involving amorphous oxides composed of heavy-metal cations with ͑n −1͒d 10 ns 0 ͑n ജ 4͒ electronic configurations.
High mobility, n-type transparent thin-film transistors ͑TTFTs͒ with a zinc indium oxide ͑ZIO͒ channel layer are reported. Such devices are highly transparent with ϳ85% optical transmission in the visible portion of the electromagnetic spectrum. ZIO TTFTs annealed at 600°C operate in depletion-mode with threshold voltages −20 to −10 V and turn-on voltages ϳ3 V less than the threshold voltage. These devices have excellent drain current saturation, peak incremental channel mobilities of 45-55 cm 2 V −1 s −1 , drain current onto off ratios of ϳ10 6 , and inverse subthreshold slopes of ϳ0.8 V / decade. In contrast, ZIO TTFTs annealed at 300°C typically operate in enhancement-mode with threshold voltages of 0-10 V and turn-on voltages 1-2 V less than the threshold voltage. These 300°C devices exhibit excellent drain-current saturation, peak incremental channel mobilities of 10-30 cm 2 V −1 s −1 , drain current onto off ratios of ϳ10 6 , and inverse subthreshold slopes of ϳ0.3 V / decade. ZIO TTFTs with the channel layer deposited near room temperature are also demonstrated. X-ray diffraction analysis indicates the channel layers of ZIO TTFTs to be amorphous for annealing temperatures up to 500°C and polycrystalline at 600°C. Low temperature processed ZIO is an example of a class of high performance TTFT channel materials involving amorphous oxides composed of heavy-metal cations with ͑n −1͒d 10 ns 0 ͑n ജ 4͒ electronic configurations.
ZnO-channel thin-film transistor (TFT) test structures are fabricated using a bottom-gate structure on thermally oxidized Si; ZnO is deposited via RF sputtering from an oxide target, with an unheated substrate. Electrical characteristics are evaluated, with particular attention given to the extraction and interpretation of transistor channel mobility. ZnO-channel TFT mobility exhibits severe deviation from that assumed by ideal TFT models; mobility extraction methodology must accordingly be recast so as to provide useful insight into device operation. Two mobility metrics, μavg and μinc, are developed and proposed as relevant tools in the characterization of nonideal TFTs. These mobility metrics are employed to characterize the ZnO-channel TFTs reported herein; values for μinc as high as 25 cm2/V s are measured, comprising a substantial increase in ZnO-channel TFT mobility as compared to previously reported performance for such devices.
Flexible transistors were fabricated by sputter deposition of zinc tin oxide (ZTO) onto plasma-enhanced chemical vapor deposition gate dielectrics formed on flexible polyimide substrates with a blanket aluminum gate electrode. The flexible transistors exhibited high on-currents of 1mA, on/off ratios of 106, subthreshold voltage slopes of 1.6V/decade, turn-on voltages of −17V, and mobilities of 14cm2V−1s−1. Capacitance measurements indicate that the threshold voltage and subthreshold slope are primarily influenced by residual doping in the ZTO rather than by defects at the semiconductor/dielectric interface, and are useful for assessing contact resistance.
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