To improve interference robustness of wireless communication, spread spectrum techniques are often used. We use the chirp spreading technique along with FSK and PSK binary modulation schemes to obtain interference robust radio communication. The performance of chirped-FSK and chirped-PSK modulation through a white gaussian noise channel is simulated assuming a synchronized clock between transmitter and the receiver. We analyzed and simulated the error probability (BER) of the overall system in the presence of partial band of interference in the channel. The simulated BER is close to the estimated BER and they prove the superior performance of chirp-based modulation in the presence of interference.

No abstract

To reduce the energy consumption in wireless sensor network transceivers, we propose an approach which combines two tradeoffs. The first tradeoff is between the receiver sensitivity and transmitter output power. The second one is the duty cycle and data rate of the transceiver. The combined approach gives us the optimum choice of noise figure and data rate for a given application and transceiver architecture. Considering a typical transceiver architecture and perfectly synchronized system, we show that the energy consumption can indeed be reduced with this approach compared to choosing either data rate or noise figure arbitrarily. Moreover, in case of a wakeup receiver architecture and slot based MAC protocol, applying this method, we show that there is a different combination of optimum data rate and noise figure value for the wakeup receivers to minimize the wakeup energy.Index terms-Energy, wireless sensor network, noise figure, data rate, duty-cycled radio.I.

No abstract

Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture ("ring counter") over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.

In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180nm as well as 90nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.Index Terms-tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit.

No abstract

No abstract