A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative "iterative" harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS.Measurements show 34 dB gain, 4 dB NF, and +3 5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order 60 dB over 40 chips, while the digital AIC technique achieves 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.Index Terms-Adaptive interference cancellation, adaptive signal processing, baseband processing, blocker, blocker filtering, CMOS, cross-correlation, digitally assisted, digitally enhanced, harmonic mixing, harmonic rejection, interference mitigation, linearity, LMS, low-noise amplifier (LNA), low-noise transconductance amplifier (LNTA), mismatch, multiphase, multiphase clock, nonlinearity, out-of-band interference, passive mixer, polyphase, receiver, robust receiver, SAW-less, software radio (SWR), software-defined radio (SDR), switching mixer, wideband receiver. A. Out-of-Band NonlinearityNonlinearity may generate intermodulation and harmonic distortion falling on top of the desired signal, or may desensitize a receiver due to blockers and produce cross modulation [10]. Without sufficient RF band-selection filtering, the out-of-band linearity can become the bottleneck since OBI is much stronger than IBI. A wideband LNA as used in [1] and [2] amplifies the desired signal and undesired wideband interference with equal 0018-9200/$26.00
In a software-defined radio (SDR) receiver it is desirable to minimize RF bandfiltering for flexibility, size and cost reasons, but this leads to increased outof-band interference (OBI). Besides harmonic and intermodulation distortion (HD/IMD), OBI can also lead to blocking and harmonic mixing. A wideband LNA [1, 2] amplifies signal and interference with equal gain. Even a low gain of 6dB can clip 0dBm OBI to a 1.2V supply, blocking the receiver. Hard-switching mixers not only translate the wanted signal to baseband but also the interference around LO harmonics. Harmonic rejection (HR) mixers have been used [3,1,4], but are sensitive to phase and gain mismatch. Indeed the HR in [4] shows a large spread, whereas other work only shows results from one chip [3,1]. This paper describes techniques to relax blocking and HD/IMD, and make HR robust to mismatch.
High linearity CMOS radio receivers often exploit linear V-I conversion at RF, followed by passive down-mixing and an OpAmp-based Transimpedance Amplifier at baseband. Due to nonlinearity and finite gain in the OpAmp, virtual ground is imperfect, inducing distortion currents. This paper proposes a negative conductance concept to cancel such distortion currents. Through a simple intuitive analysis, the basic operation of the technique is explained. By mathematical analysis the optimum negative conductance value is derived and related to feedback theory. In-and out-of-band linearity, stability and Noise Figure are also analyzed. The technique is applied to linearize an RF receiver, and a prototype is implemented in 65 nm technology. Measurement results show an increase of in-band IIP 3 from 9dBm to >20dBm, and IIP2 from 51 to 61dBm, at the cost of increasing the noise figure from 6 to 7.5dB and <10% power penalty. In 1MHz bandwidth, a Spurious-Free Dynamic Range of 85dB is achieved at <27mA up to 2GHz for 1.2V supply voltage.
Recently several CMOS software-defined radio (SDR) demonstrators have been presented using mixers as the wideband downconverter [1,2]. Meanwhile, the feasibility of RF samplers as downconverter has also been demonstrated [3,4]. These samplers allow for more discrete-time (DT) and digital signal processing, and are therefore better suited for advanced CMOS technologies. However, samplers suffer from several problems if used in a wideband SDR. Charge sampling [3] gives a conversion gain which is inversely proportional to frequency [5]. Voltage sampling [4] doesn't have this problem, but suffers from wideband noise folding. In both cases, RF pre-filters are needed to prevent interferers around harmonics of the sampling clock from folding back to the baseband. In this paper, we propose a DT harmonic-rejection (HR) mixing architecture that relaxes RF filter requirements and reduces the noise folding. The proposed SDR downconverter is aimed for the DVB-H standard (470 to 862MHz) and for emerging cognitive radio applications in the 200-to-900MHz band, which suffer from 3 rd and 5 th harmonic mixing. Figure 17.1.1 shows the architecture of the IC. An inverter-based RF-amplifier (RFA) drives a passive switchedcapacitor (SC) core consisting of three stages. The first stage is effectively an oversampler, with f s =8f c (f s is the sampling frequency and f c is the carrier frequency). The second stage consists of I/Q DT mixers for downconversion. The third stage is a low-pass IIR filter. The zero-IF quadrature outputs are buffered via source followers. A clock generator is implemented using a divide-by-4 circuit and NOR gates to generate 8-phase 12.5%-duty-cycle fullswing clocks to drive the sampling circuitry. An external sinusoidal differential master clock is used with a frequency of 4f c. Note that an LNA is not included in this design.
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