A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

Abstract

Recently several CMOS software-defined radio (SDR) demonstrators have been presented using mixers as the wideband downconverter [1,2]. Meanwhile, the feasibility of RF samplers as downconverter has also been demonstrated [3,4]. These samplers allow for more discrete-time (DT) and digital signal processing, and are therefore better suited for advanced CMOS technologies. However, samplers suffer from several problems if used in a wideband SDR. Charge sampling [3] gives a conversion gain which is inversely proportional to frequency [5]. Voltage sampling [4] doesn't have this problem, but suffers from wideband noise folding. In both cases, RF pre-filters are needed to prevent interferers around harmonics of the sampling clock from folding back to the baseband. In this paper, we propose a DT harmonic-rejection (HR) mixing architecture that relaxes RF filter requirements and reduces the noise folding. The proposed SDR downconverter is aimed for the DVB-H standard (470 to 862MHz) and for emerging cognitive radio applications in the 200-to-900MHz band, which suffer from 3 rd and 5 th harmonic mixing. Figure 17.1.1 shows the architecture of the IC. An inverter-based RF-amplifier (RFA) drives a passive switchedcapacitor (SC) core consisting of three stages. The first stage is effectively an oversampler, with f s =8f c (f s is the sampling frequency and f c is the carrier frequency). The second stage consists of I/Q DT mixers for downconversion. The third stage is a low-pass IIR filter. The zero-IF quadrature outputs are buffered via source followers. A clock generator is implemented using a divide-by-4 circuit and NOR gates to generate 8-phase 12.5%-duty-cycle fullswing clocks to drive the sampling circuitry. An external sinusoidal differential master clock is used with a frequency of 4f c. Note that an LNA is not included in this design.

A Spectrum Sensing Technique for Cognitive Radios in the Presence of Harmonic Images

“…. , c ∞ }: (4) By combining (3) and (4), an expression is obtained that shows the relation of the downmixed products to the basebandequivalent signals z p (t) and the Fourier coefficients of the mixer's LO waveform:…”

A tunable 300–800MHz RF-sampling receiver achieving 60dB harmonic rejection and 0.8dB minimum NF in 65nm CMOS

“…1, the RFSD [5] consists of S/H, I/Q DT mixers with 3 rd and 5 th HR, a divide-by-4 generating an 8-phase 1/8-duty-cycle LO, and IIR low-pass filters. The RFA in [5] is equivalent to the LNA 2 nd stage in this paper, but its topology was not shown. The quadrature outputs are buffered via source followers, only for testing.…”

“…RF SAW filters can help but compromise the flexibility of a SDR receiver and are also bulky and costly. Recently, a flexible and wideband harmonic rejection (HR) technique has been proposed for RF-sampling receivers, via a discrete-time (DT) mixing architecture [5]. However, the achieved 3 rd and 5…”

“…We aim at a receiver covering 300MHz to 800MHz (DVB-H band and TV white-space bands for cognitive radio) in two sub-bands. This paper discusses the design of the receiver with an emphasis on the filter/LNA part while the sampling downconverter was described in [5].…”

A Two-Stage Approach to Harmonic Rejection Mixing Using Blind Interference Cancellation

“…This technique has been successfully applied in CMOS transmitters [3] and in receivers [4], [5]. In [4], the average harmonic rejection across 10 chips is around 40 dB and in [5] the HR ratio is around 42 dB. This is often not enough.…”