An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.Bonding of metal surfaces is extensively used for MEMS sealing, power devices, heat dissipation or 3D interconnections. For these applications, techniques such as thermo compression, with or without eutectic alloys or adhesives layers, bumps with low temperature solders or direct bonding are extensively implemented techniques. 1-7 Moreover, for More Moore and More than Moore applications, low temperature bonding and metal bonding are becoming the main drivers of the latest developments. As copper is the main metal used for CMOS interconnects, a high-density Cu interconnection between layer structures, is expected for future three-dimensional integration of electronic devices fabricated on the basis of different technology/ design concepts. In this paper, an overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD and TEM analysis. Dedicated characterization techniques for such bonding are presented. Hybridization Techniques ReviewCopper is the most (compared to other possible bonding metals) promising candidate for 3D integration technology either for TSV filling or interstata hybridizing. The main reasons of this choice is the widely use of copper in semiconductor device industries and the cost of ownership. On the other hand, the choice of the metal bonding technique is still an open question. Bonding anneal temperature, duration of the annealing, need of an underfill, size and pitch of the interconnect pads, availability of the technique for wafer bonding or die bonding are key parameters of the final choice. The main studied bonding techniques can be divided into two groups: with and without thermal compression.Bonding with a compression force: Diffusion bonding.-The thermal compression bonding is a well known technique. 8-10 Wafers or dies are pressed together with a controlled force in a bonding tool, while heating is applied (400 C) to allow the bonding diffusion mechanism. Thanks to the compression force, the surfaces roughness is not a limiting factor as the surface asperities are deformed at the bonding interface, therefore surfaces with a roughness in the range of 5 nm can be used. Copper oxide should be avoided or removed right before ...

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This paper presents the latest results on electrical characterization of wafer to wafer structures made by direct copper bonding. The bonding was achieved at room temperature, atmospheric pressure and ambient air, followed by a 200°C or 400°C post bonding anneal. Description of the 3D integration process and the test-vehicle (which is used to evaluate the impact of bonding on Cu/Cu interface reliability) are described. Daisy chains from hundreds to tens of thousand connexions were tested and showed a resistance of 79.5 mΩ per node (bonding interface + Cu lines), and a specific contact resistance of the bonding around 22.5 mΩ.µm² was extracted. These results present patterned Cu/SiO 2 direct bonding as a promising solution for high density 3D integrated stacks. IntroductionThree-dimensional (3D) integration appears as a good alternative solution to overcome the limitations of component miniaturisation (Moore's law) and to allow the increase of the devices performance [1,2]. Offering heterogeneous integration, shorter interconnection length and lower cost, this technology can address both More Moore and More than Moore applications [3]. A gain on production costs is also expected. To achieve a 3D component, some technological key steps have to be perfectly mastered: wafer and chip aligned bonding, thinning and handling of wafer and vertical interconnection using Through Silicon Vias (TSV) [4]. The direct metallic bonding, which is a promising solution for cost reduction, presents the advantage to allow a high density vertical electrical contact with a high bonding strength. Furthermore, it is also a one via technology. Results on direct copper bonding have already been published as a promising way to interconnect strata [5].A mask set of Test-Vehicle (TV) was specifically designed to allow the electrical full characterization of the direct copper bonding. The TV was created in order to allow both wafer-to-wafer (WtW) and chip-to-wafer (CtW) bonding.

International audienceWe present a free-space optomechanical system operating in the 1-K range. The device is made ofa high mechanical quality factor micropillar with a high-reflectivity optical coating atop, combinedwith an ultra-small radius-of-curvature coupling mirror to form a high-finesse Fabry-Perot cavityembedded in a dilution refrigerator. The cavity environment as well as the cryostat have beendesigned to ensure low vibrations and to preserve micron-level alignment from room temperatur