Full characterization of Cu/Cu direct bonding for 3D integration

Abstract

This paper presents the latest results on electrical characterization of wafer to wafer structures made by direct copper bonding. The bonding was achieved at room temperature, atmospheric pressure and ambient air, followed by a 200°C or 400°C post bonding anneal. Description of the 3D integration process and the test-vehicle (which is used to evaluate the impact of bonding on Cu/Cu interface reliability) are described. Daisy chains from hundreds to tens of thousand connexions were tested and showed a resistance of 79.5 mΩ per node (bonding interface + Cu lines), and a specific contact resistance of the bonding around 22.5 mΩ.µm² was extracted. These results present patterned Cu/SiO 2 direct bonding as a promising solution for high density 3D integrated stacks. IntroductionThree-dimensional (3D) integration appears as a good alternative solution to overcome the limitations of component miniaturisation (Moore's law) and to allow the increase of the devices performance [1,2]. Offering heterogeneous integration, shorter interconnection length and lower cost, this technology can address both More Moore and More than Moore applications [3]. A gain on production costs is also expected. To achieve a 3D component, some technological key steps have to be perfectly mastered: wafer and chip aligned bonding, thinning and handling of wafer and vertical interconnection using Through Silicon Vias (TSV) [4]. The direct metallic bonding, which is a promising solution for cost reduction, presents the advantage to allow a high density vertical electrical contact with a high bonding strength. Furthermore, it is also a one via technology. Results on direct copper bonding have already been published as a promising way to interconnect strata [5].A mask set of Test-Vehicle (TV) was specifically designed to allow the electrical full characterization of the direct copper bonding. The TV was created in order to allow both wafer-to-wafer (WtW) and chip-to-wafer (CtW) bonding.

Voiding Phenomena in Copper-Copper Bonded Structures: Role of Creep

“…In this new specific configuration, copper thin films allows wafers or die level assemblies exhibiting high bonding strength and good interlayer electrical conduction reducing interconnection delays and increasing overall performances. 4,5 Various direct wafer bonding processes allow joining copper surfaces in the [20-400…”

(Invited) An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization

“…These values of resistance and specific resistance show that there is an insignificant impact of the bonding interface. And that the bonded structures have almost the same electrical behavior as copper line bulk without an interface [30].…”

“…A total chain resistance of 2.34 kΩ is measured for this daisy chain, which corresponds to a resistance of 79.5 mΩ per node (node = bonding interface + Cu lines) ( Figure 15). Comparing the experimental with the theoretical calculation of the resistance per node (that leads to a value of 77 mΩ), a difference of 2.5 mΩ is obtained [30].…”

Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integration

“…In terms of electrical characterization, a specific contact resistance of 0.5Ω.µm² for a 10x10µm²contact area after annealing at 200°C and 400°C for 2h was achieved ( Figure 3b) [6,11]. The resistance per node extracted from a ~30K daisy chain after 400°C post-bond anneal showed negligible resistance induced by bonding [11,12]. In addition, initial reliability data based on electromigration (EM) testing shows that the bonded metallic interfaces are not the dominant path for the EM phenomena [13].…”