An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization

Abstract

An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.Bonding of metal surfaces is extensively used for MEMS sealing, power devices, heat dissipation or 3D interconnections. For these applications, techniques such as thermo compression, with or without eutectic alloys or adhesives layers, bumps with low temperature solders or direct bonding are extensively implemented techniques. 1-7 Moreover, for More Moore and More than Moore applications, low temperature bonding and metal bonding are becoming the main drivers of the latest developments. As copper is the main metal used for CMOS interconnects, a high-density Cu interconnection between layer structures, is expected for future three-dimensional integration of electronic devices fabricated on the basis of different technology/ design concepts. In this paper, an overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD and TEM analysis. Dedicated characterization techniques for such bonding are presented. Hybridization Techniques ReviewCopper is the most (compared to other possible bonding metals) promising candidate for 3D integration technology either for TSV filling or interstata hybridizing. The main reasons of this choice is the widely use of copper in semiconductor device industries and the cost of ownership. On the other hand, the choice of the metal bonding technique is still an open question. Bonding anneal temperature, duration of the annealing, need of an underfill, size and pitch of the interconnect pads, availability of the technique for wafer bonding or die bonding are key parameters of the final choice. The main studied bonding techniques can be divided into two groups: with and without thermal compression.Bonding with a compression force: Diffusion bonding.-The thermal compression bonding is a well known technique. 8-10 Wafers or dies are pressed together with a controlled force in a bonding tool, while heating is applied (400 C) to allow the bonding diffusion mechanism. Thanks to the compression force, the surfaces roughness is not a limiting factor as the surface asperities are deformed at the bonding interface, therefore surfaces with a roughness in the range of 5 nm can be used. Copper oxide should be avoided or removed right before ...

Kinetics of low temperature direct copper–copper bonding

“…Figure 5 shows bonding toughness evolution with storage time at room temperature for copper layer deposited by ECD and PVD technique. Assembly performed with ECD copper layers exhibit an increase of bonding toughness until 2.5 J/m 2 after 120 days of storage in good agreement with literature results (Di Cioccio et al 2011). Samples which are performed with PVD copper layers exhibit low bonding toughness evolution from 0.5 to 0.7 J/m 2 after 120 days of storage.…”

“…It has been already reported that copper-copper bonding strength performed at room temperature (20 °C) in cleanroom atmosphere increases with regards to storage time (Di Cioccio et al 2011). In this paper, we show that this bonding strengthening is not always observed.…”

“…The mechanism of the bonding strengthening in the (RT, 100 °C) temperature range is already reported as a metal oxidation at the bonding interface during storage or annealing at low temperature (Di Cioccio et al 2011). At room temperature, they show that oxidation leads especially to a bonding toughness increase until 2.5 J/m 2 which is correlated to the formation of a 4-nm-thick copper oxide layer of at the bonding interface (observed by High Resolution Transmission Electron Microscopy-HRTEM).…”

“…Since copper is widely used in CMOS interconnects for its low electrical resistivity and high electromigration resistance (Ryan et al 1995), direct copper-copper bonding at low temperature is a promising option for implementation of three-dimension integrated circuits (3D-IC) or micro electrical mechanical systems (MEMS). Various bonding techniques exist to join copper surfaces in the temperature range below 400 °C involving for example a uniaxial compressive force (Chen et al 2005), a surface activation by ion bombardment (Shigetou and Suga 2009), a surface passivation by an organic monolayer (Tan et al 2009) or chemical mechanical polishing (CMP) steps (Di Cioccio et al 2011). More specifically, the direct bonding technique involving CMP surface activation consists to put into contact two mirror-polished wafers which are held together by attractive forces at room temperature (RT) without any additional materials.…”

Voiding Phenomena in Copper-Copper Bonded Structures: Role of Creep

“…Due to the high-hydrophilic behavior of copper surfaces after CMP treatment, some water monolayers are trapped at the bonding interface, react with metal at room temperature and create a 4 nm-thick copper oxide layer which definitively seals bonding inter- face without any volume trapped at the bonding interface. 22,23 In our study, although voids are observed in all studied cases, we assume that process parameters and surface properties result in complete bonding interface sealing: voiding appearance in bonded copper layers cannot be due to free volume trapped during bonding processes.…”