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Processing issues for the fabrication of capacitive micromachined ultrasonic transducer (cMUT) arrays have been studied using surface micromachining. This work focuses on the critical steps of process fabrication such as membrane formation, sacrificial layer properties and vacuum sealing performance of cavity. We describe a four-mask process for the realization of sealed cMUT. We demonstrate that the use of a sacrificial layer with a columnar structure gives a fast etching rate (29 nm s −1 ) in a buffered hydrofluoric acid solution. The mechanical stress of LPCVD silicon nitride (SiN x ), used as membrane, was evaluated. We compared the vacuum sealing performance of different materials in order to find the best material in terms of lateral deposition inside the cavity. Functional transducers have been obtained. We proposed an electrical test in order to evaluate the vacuum sealing of the cavity based on the collapse voltage determination. Laser interference measurements were used to characterize the dynamic displacement of the membrane.

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Lateral gettering has been studied by introducing cavities in the periphery of large active devices. Cavities were induced by helium implantation followed by a thermal treatment on samples previously contaminated by iron. Those cavities are known to be efficient to trap metallic impurities in silicon by chemisorption. The iron distribution in samples of 6×6 mm2 area has been monitored by measuring current versus voltage characteristics and interstitial iron concentrations by deep level transient spectroscopy on Schottky diodes uniformly distributed. A symmetrical iron distribution has been observed with a decreasing concentration close to the gettering region. This lateral gettering is enhanced with increasing thermal budget. Extensions of several millimeters can be obtained allowing applications in power device technology.

We propose a new methodology for lifetime determination of PZT capacitors, based on accelerated tests performed at low voltages and high temperatures. We believe that such a methodology is the only way to characterize the relevant failure mechanism for Time-Dependent Dielectric Breakdown of PZT capacitors. The capacitors lifetime at operating conditions is found to exceed 20 years. PURPOSEOver the last few years, thin films of PbZr x Ti 1−x O 3 (PZT) have been the focus of extensive research for filtering and decoupling capacitor applications. The essential requirements for such applications include a high dielectric constant, low dissipation factor, low leakage current, and acceptable capacitor lifetime. Among these properties, the reliability and the comprehension of failure mechanisms have already been investigated [1-4], but we believe that this issue needs to be explored further. From our first Wafer Level Reliability (WLR) results, we identified two different degradation mechanisms, depending on the applied electrical field [5]. In this paper, we expose the statistical data representative of these two mechanisms and we propose a testing methodology which enables to characterize only the relevant mechanism for lifetime extrapolation. This methodology is based on cumulated temperature and voltage accelerations. Our reliability model, which describes the dielectric lifetime as a function of voltage and temperature, is discussed in the last section.