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A detailed comparison is made between theory and experiment for the low-temperature mobility of holes in gated oxide, coherently strained Si/SiGe heterostructures. We conclude that the mobility is mainly limited by interface impurities, conventional surface roughness and strain fluctuations; by contrast, we argue that alloy scattering is comparatively weak. Comments regarding possible mobility degradation due to oxide formation are also made.

V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control.We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.