Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

Dal, M.J.H. van; Collaert, N.; Doornbos, G.; Vellianitis, G.; Curatola, G.; Pawlak, Bartek; Duffy, Ray; Jonville, C.; Degroote, B.; Altamirano, E.; Kunnen, E.; Demand, M.; Beckx, S.; Vandeweyer, T.; Delvaux, Christie; Leys, F.; Hikavyy, Andriy; Rooyackers, R.; Kaiser, M.; Weemaes, R. G. R.; Biesemans, S.; Jurczak, M.; Anil, K.G.; Witters, L.; Lander, R.J.P.

doi:10.1109/vlsit.2007.4339747

Cited by 68 publications

(47 citation statements)

References 2 publications

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“…Thus, despite the presence of a lattice template at the bottom of the fin, recrystallization was highly defected, which produced an increase of the on-resistance of the final device. 13,14 On the contrary, in bulk silicon systems, where regrowth occurs perpendicular instead of parallel to the surfaces/interfaces, recrystallization is almost perfect. 7 Figure 3 shows several snapshots taken during a MD simulation of a 10 nm wide Si fin annealing surrounded by amorphous material.…”

Section: Resultsmentioning

confidence: 99%

“…9,12 These regrowth features, which are more acute in narrower structures, are serious concerns because of the degradation of device performance and variability. 13,14 In a previous work, we showed that the atomistic simulation technique known as MD was able to reproduce the features observed in experiments. 15 These results were recently confirmed by other authors also using MD techniques.…”

Section: Introductionmentioning

confidence: 94%

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Molecular dynamics simulation of the regrowth of nanometric multigate Si devices

Marqués

Pelaz

Santos

et al. 2012

Journal of Applied Physics

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We use molecular dynamics (MD) simulation techniques to study the regrowth of nanometric multigate Si devices, such as fins and nanowires, surrounded by free surfaces and interfaces with amorphous material. Our results indicate that atoms in amorphous regions close to lateral free surfaces or interfaces rearrange at a slower rate compared to those in bulk due to the discontinuity of the lateral crystalline template. Consequently, the recrystallization front which advances faster in the device center than at the interfaces adopts new orientations. Regrowth then proceeds depending on the particular orientation of the new amorphous/crystal interfaces. In the particular case of (110) oriented fins, the new amorphous/crystal interfaces are aligned along the (111) direction, which produces frequent twining during further regrowth. Based on our simulation results, we propose alternatives to overcome this defected recrystallization in multigate structures: device orientation along (100) to prevent the formation of limiting {111} I amorphous/crystal interfaces and presence of a crystalline seed along the device body to favor regrowth perpendicular to the lateral surfaces/interfaces rather than parallel to them. (C) 2012 American Institute of Physics. [doi :10.1063/1.3679126

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 94%

Molecular dynamics simulation of the regrowth of nanometric multigate Si devices

Marqués

Pelaz

Santos

et al. 2012

Journal of Applied Physics

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“…We obtained highly scaled and strained FinFETs from NXP-TSMC Research, Leuven, Belgium [19] and measured their leakage characteristics. Section 2.1 discusses the amount and orientation of the strain in these devices.…”

Section: Strain In Finfetsmentioning

confidence: 99%

“…Note that the crystal coordinate system is also indicated. The 65 nm high silicon fins measured in this work, see figure 2.3, are covered by a stack of 1 nm thick silicon dioxide (SiO 2 ) and 1.7 nm thick high-κ hafnium silicate (HfSiO) [19]. The composition is Hf 0.4 Si 0.6 O.…”

Section: Strain Modellingmentioning

confidence: 99%

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Tailoring strain in microelectronic devices

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Silicon Nanowire Charge‐Trap Memory Incorporating Self‐Assembled Iron Oxide Quantum Dots

Huang

Heath

2012

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Charge‐trap non‐volatile memory devices based upon the precise integration of quantum dot storage elements with silicon nanowire field‐effect transistors are described. Template‐assisted assembly yields an ordered array of FeO QDs within the trenches that separate highly aligned SiNWs, and injected charges are reversibly stored via Fowler–Nordheim tunneling into the QDs. Stored charges shift the transistor threshold voltages, providing the basis for a memory device. Quantum dot size is found to strongly influence memory performance metrics.

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Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

Cited by 68 publications

References 2 publications

Molecular dynamics simulation of the regrowth of nanometric multigate Si devices

Molecular dynamics simulation of the regrowth of nanometric multigate Si devices

Tailoring strain in microelectronic devices

Silicon Nanowire Charge‐Trap Memory Incorporating Self‐Assembled Iron Oxide Quantum Dots

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