A study has been conducted of the effects of deposition conditions on the radiation hardness of borophosphosilicate glass (BPSG). Films deposited by two common deposition techniques were evaluated using gamma cell testing, electron spin resonance (ESR), and capacitance voltage (CV) measurements. The results indicate that two stoichiometrically similar films can differ greatly in radiation tolerance depending on the deposition conditions.
A 1.2 pm CMOS production process was adapted to produce a 64K CMOS fusible-link Programmable Read-only Memory (PROM) for space applications. The circuit requirement of less than 50 nS access time combined with the need for 9 volt single pulse programming of the fusible links and radiation tolerance to levels over 300 Krad(Si) made close collaboration between design engineering, reliability engineering, and device engineering essential for a successful project. A vertical NPN bipolar transistor was integrated into a standard CMOS process to be used for programming and reading the fuses. The device characteristics were carefully matched to the product speed and programmability requirements. The NPN device was optimized for radiation performance. Successful development required extensive use of process and device modeling, test structure design and measurement, and experimental design methods.
High density, low power 180nm and 130nm CMOS SRAMs have been manufactured on bulk silicon wafers using a modified CMOS commercial process that hardens the junction isolation and has demonstrated latchup immunity at temperatures >200°C. TCAD simulations confirmed by high temperature testing indicate that a latch up free performance of SRAMs manufactured on bulk silicon modified by the HardSIL™ technology will easily extrapolate to 250°C. These process modifications result in significantly more robust CMOS circuits making them more suitable for highly reliable operations in extreme environments – such as radiation and high temperature. The unique capability of HardSIL™ technology to enhance existing IC products has demonstrated excellent results with several commercial circuits. This new approach enables the conversion of commercial off the shelf (COTS) circuits to hardened hi-rel commercial circuits with dramatically improved survivability to either radiation or high temperatures. Latchup immunity has been demonstrated on two high-density bulk silicon CMOS SRAMs: a 16Mbit asynchronous SRAM manufactured at the 180nm design node and an 8Mbit dual port synchronous SRAM manufactured at 130nm. Both parts were produced in a high-volume, low-defect commercial CMOS fabrication facility in the USA. The SRAM parts were packaged in ceramic packages and characterized at temperatures ranging from 25°C to 225°C. Characterization data indicates both excellent static leakage and dynamic circuit performance for both SRAMs at these elevated temperatures. Device test structures designed with typical layout spacing rules were evaluated to quantify latchup and isolate the various leakage mechanisms. Detailed results for these test structures are presented and compared to the SRAMs using the modified HardSIL™ process.
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