High density, low power 180nm and 130nm CMOS SRAMs have been manufactured on bulk silicon wafers using a modified CMOS commercial process that hardens the junction isolation and has demonstrated latchup immunity at temperatures >200°C. TCAD simulations confirmed by high temperature testing indicate that a latch up free performance of SRAMs manufactured on bulk silicon modified by the HardSIL™ technology will easily extrapolate to 250°C. These process modifications result in significantly more robust CMOS circuits making them more suitable for highly reliable operations in extreme environments – such as radiation and high temperature. The unique capability of HardSIL™ technology to enhance existing IC products has demonstrated excellent results with several commercial circuits. This new approach enables the conversion of commercial off the shelf (COTS) circuits to hardened hi-rel commercial circuits with dramatically improved survivability to either radiation or high temperatures. Latchup immunity has been demonstrated on two high-density bulk silicon CMOS SRAMs: a 16Mbit asynchronous SRAM manufactured at the 180nm design node and an 8Mbit dual port synchronous SRAM manufactured at 130nm. Both parts were produced in a high-volume, low-defect commercial CMOS fabrication facility in the USA. The SRAM parts were packaged in ceramic packages and characterized at temperatures ranging from 25°C to 225°C. Characterization data indicates both excellent static leakage and dynamic circuit performance for both SRAMs at these elevated temperatures. Device test structures designed with typical layout spacing rules were evaluated to quantify latchup and isolate the various leakage mechanisms. Detailed results for these test structures are presented and compared to the SRAMs using the modified HardSIL™ process.
This paper will describe the development and testing of a new ARM© Cortex©-M based microcontroller for high temperature electronic systems. High temperature and electrical overstresses can cause latch-up in CMOS devices that will interfere with normal device operation or destroy the device. For reliable operation in the downhole drilling environment it was necessary to immunize this device against latch-up using an innovation processing technique. HARDSIL® technology that allows reliable latch-up free operation at extreme temperatures will be described. Details on the qualification and testing of the product to ensure that it meets the challenging environment will also be discussed. This includes electrical testing and temperature cycling testing to ensure that the different package options for the silicon device are mechanically sound in a high temperature environment that exposes the silicon and packaging materials to thermal cycling. The ecosystem for the microcontroller will also be discussed – hardware and software development tools are required to optimize the use of the device in extreme temperature embedded systems. An ecosystem of components is also required to operate with the microcontroller in the high temperature harsh environment.
VORAGO Technologies has developed a pair of ARM Cortex M0 MCUs designed from the ground up to be high temperature capable. One of these devices is specifically developed for high temperature applications, the other adds capabilities that make it suitable for use in high radiation environments as well. These devices are fabricated using a modified version of commercial bulk 130nm CMOS technology utilizing our HARDSIL® technology, which provides immunity to the increased effects of latchup and EOS encountered at higher application temperatures. In addition to the processor these devices include features more typical of low temperature SoCs including on-chip memory, timers, and communications peripherals. In addition to the ceramic package and die format typically utilized at high temperature, a new lower-cost plastic package is available that has been characterized at higher temperatures. These devices have been characterized at temperatures up to 200C and results showing the latchup behavior and device performance are provided. Some of the tradeoffs involved in creating such devices are discussed, as well as some of the similarities and tradeoffs in creating a radiation hardened devices vs. a high temperature device.
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